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参数资料
| 型号： | FAN5904UC01X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 21/23页 |
| 文件大小： | 0K |
| 描述： | IC CONV BUCK W/BYPASS 16-WLCSP |
| 标准包装： | 1 |
| 应用： | 转换器，3G，3.5G，4G RF 功率放大器 |
| 输入电压： | 2.7 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 供应商设备封装： | 16-WLCSP |
| 包装： | 标准包装 |
| 其它名称： | FAN5904UC01XFSDKR |
Filter VCON
Assembly
VCON is the analog control pin of the DC-DC and should be
connected to an external Digital-to-Analog Converter (DAC).
It is recommended to add up to 470 pF decoupling
capacitance between VCON and AGND to filter DAC noise.
This capacitor also helps protect the DAC from the DC-DC
high-frequency switching noise inherently coupled through
the VCON pin. The value of the capacitor must be selected
according to the DAC performance since it could limit the
DAC output voltage slew rate. 470 pF is typically used.
Any noise on the V CON input is transferred to V OUT with a gain
of two and a half (2.5). If the DAC output is noisy, a series
resistor may be inserted between the DAC output and the
capacitor to form an RC filter.
Follow these guidelines:
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Use lead-free solder reflow temperature profile.
Use metal-filled or solder-filled vias, if available.
Poor soldering can cause low DC-DC conversion
efficiency. If the efficiency is low, X-ray the solder
connections to verify their integrity.
PVIN and PGND must be routed with the widest and
shortest traces possible. It is acceptable for the traces
connecting the inductor to be long rather than having
long PVIN or PGND traces.
Ensure that the routing loop, PVIN – PGND – VOUT is
as short as possible.
Place PGND on the top layer and connect it to the
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Use a low noise source or a driver with good PSRR to
AGND ground plane next to C out using several vias.
generate V CON .
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The SW node is a source of electrical switching noise.
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The V CON driver must be referenced to AGND.
Do not route it near the VCON pin.
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V CON routing must be protected against PVIN, SW, and
PGND signals, as well as other noisy signals. Use
AGND shielding for better isolation.
Be sure the DAC output can drive the capacitor on
VCON. It may be necessary to insert a low-value
resistor to ensure DAC stability while not slowing V CON
fast transition times.
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Two small vias are used to connect the SW node to the
inductor L1. Use solder-filled vias, if available.
The connection from C OUT to FB should be wide to
minimize the Bypass Mode voltage drop and the series
inductance. Even if the current in Bypass Mode is small,
keep this trace short and at least 5 mm wide.
The AGND ground plane should not be broken into
No Floating Inputs
pieces. Ground currents must have a direct, wide path
from input to output.
The FAN5904 does not have internal pull-down resistors on
its inputs. Therefore, unused inputs should not be left
floating and should be pulled HIGH or LOW.
PCB Layout and Component Placement
The key point in the placement is the power ground
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PGND connection shared between the FAN5904, C1,
and C2. This minimizes the parasitic inductance of the
switching loop paths.
Place the inductor away from the feedback pins to
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prevent unpredictable loop behavior.
Ensure the traces are wide enough to handle the
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maximum current value, especially in Bypass mode.
Ensure the vias are able to handle the current density.
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Use filled vias if available.
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Refer to Fairchild’s application note: AN9726 — The
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Each capacitor should have at least two dedicated
ground vias. Place vias within 0.1 mm of the capacitors.
Importance of PCB Design for FAN5903 and FAN5904.
Figure 59. Example PCB Layout of FAN5904
? 2011 Fairchild Semiconductor Corporation
FAN5904 ? Rev. 3.0.7
21
www.fairchildsemi.com
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