参数资料
型号: FDD6796A
厂商: Fairchild Semiconductor
文件页数: 2/6页
文件大小: 0K
描述: MOSFET N-CH 25V 20A DPAK
产品目录绘图: DPAK, TO-252(AA)
标准包装: 1
系列: PowerTrench®
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 25V
电流 - 连续漏极(Id) @ 25° C: 20A
开态Rds(最大)@ Id, Vgs @ 25° C: 5.7 毫欧 @ 20A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 34nC @ 10V
输入电容 (Ciss) @ Vds: 1780pF @ 13V
功率 - 最大: 3.7W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: D-Pak
包装: 标准包装
产品目录页面: 1605 (CN2011-ZH PDF)
其它名称: FDD6796ADKR
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
? BV DSS
? T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
V DS = 20 V, V GS = 0 V
V GS = ±20 V, V DS = 0 V
25
16
1
±100
V
mV/°C
μ A
nA
On Characteristics
V GS(th)
? V GS(th)
? T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
I D = 250 μ A, referenced to 25 °C
1.0
1.9
-6
3.0
V
mV/°C
V GS = 10 V, I D = 20 A
4.3
5.7
r DS(on)
Static Drain to Source On Resistance
V GS = 4.5 V, I D = 15.2 A
11.1
15.0
m ?
V GS = 10 V, I D = 20 A, T J = 150 °C
6.5
8.6
g FS
Forward Transconductance
V DS = 5 V, I D = 20 A
118
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = 13 V, V GS = 0 V,
f = 1 MHz
1336
298
266
1.2
1780
400
400
pF
pF
pF
?
Switching Characteristics
t d(on)
Turn-On Delay Time
8
16
ns
t r
t d(off)
t f
Q g
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
V DD = 13 V, I D = 20 A,
V GS = 10 V, R GEN = 6 ?
V GS = 0 V to 10 V
7
19
4
24
14
34
10
34
ns
ns
ns
nC
Q g
Q gs
Total Gate Charge
Gate to Source Charge
V GS = 0 V to 5 V
V DD = 13 V,
I D = 20 A
14
4.0
20
nC
nC
Q gd
Gate to Drain “Miller” Charge
5.7
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0 V, I S = 3.1 A
V GS = 0 V, I S = 20 A
(Note 2)
(Note 2)
0.8
0.9
1.2
1.3
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = 20 A, di/dt = 100 A/ μ s
15
4
27
10
ns
nC
Notes :
1: R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R θ JC is guaranteed by design while R θ JA is determined by the user’s board design.
a) 40 °C/W when mounted on a
1 in 2 pad of 2 oz copper
b) 96 °C/W when mounted on
a minimum pad
2: Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3: E AS of 40 mJ is based on starting T J = 25 ° C, L = 1 mH, I AS = 9 A, V DD = 23 V, V GS = 10 V. 100% test at L = 0.1 mH, I AS = 21 A.
?2009 Fairchild Semiconductor Corporation
FDD6796A / FDU6796A_F071 Rev.C1
2
www.fairchildsemi.com
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