参数资料
型号: FDMS3668S
厂商: Fairchild Semiconductor
文件页数: 2/16页
文件大小: 0K
描述: MOSFET N-CH 30V DUAL 8-PQFN
标准包装: 3,000
系列: PowerTrench®
FET 型: 2 N 沟道(双)非对称型
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 13A,18A
开态Rds(最大)@ Id, Vgs @ 25° C: 8 毫欧 @ 13A,10V
Id 时的 Vgs(th)(最大): 2.7V @ 250µA
闸电荷(Qg) @ Vgs: 29nC @ 10V
输入电容 (Ciss) @ Vds: 1765pF @ 15V
功率 - 最大: 1W
安装类型: 表面贴装
封装/外壳: 8-TDFN 裸露焊盘
供应商设备封装: 8-PQFN(5x6)
包装: 带卷 (TR)
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DS S
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = 250 μ A, V GS = 0 V
I D = 1 mA, V GS = 0 V
I D = 250 μ A, referenced to 25 °C
I D = 10 mA, referenced to 25 °C
V DS = 24 V, V GS = 0 V
V GS = 20 V, V DS = 0 V
V GS = 12 V, V DS = 0 V
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
30
30
16
17
1
500
100
100
V
mV/°C
μ A
μ A
nA
nA
On Characteristics
V GS(th)
Δ V GS(th )
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = 250 μ A
V GS = V DS , I D = 1 mA
I D = 250 μ A, referenced to 25 °C
I D = 10 mA, referenced to 25 °C
Q1
Q2
Q1
Q2
1.1
1.1
1.9
1.5
-6
-3
2.7
2.2
V
mV/°C
V GS = 10 V, I D = 13 A
4
8
V GS = 4.5 V, I D = 11 A
Q1
6
11
r DS(on)
Drain to Source On Resistance
V GS = 10 V, I D = 13 A , T J = 125 °C
V GS = 10 V, I D = 18 A
V GS = 4.5 V, I D = 17 A
Q2
5.7
3
3.6
8.7
5
5.2
m Ω
V GS = 10 V, I D = 18 A , T J = 125 °C
4.4
7.3
g FS
Forward Transconductance
V DS = 5 V, I D = 13 A
V DS = 5 V, I D = 17 A
Q1
Q2
62
110
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Q1:
V DS = 15 V, V GS = 0 V, f = 1 MHZ
Q2:
V DS = 15 V, V GS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
1325
1935
466
479
46
45
1765
2575
620
635
70
70
pF
pF
pF
R g
Gate Resistance
Q1
Q2
0.2
0.2
0.6
1.3
2
3
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
Q1
Q2
7.7
7.1
15
14
ns
t r
t d(off)
t f
Rise Time
Turn-Off Delay Time
Fall Time
Q1:
V DD = 15 V, I D = 13 A, R GEN = 6 Ω
Q2:
V DD = 15 V, I D = 17 A, R GEN = 6 Ω
Q1
Q2
Q1
Q2
Q1
Q2
2.2
2.7
19
25
1.8
1.9
10
10
34
40
10
10
ns
ns
ns
Q g
Total Gate Charge
V GS = 0 V to 10 V
Q1:
Q1
Q2
21
27
29
38
nC
Q g
Q gs
Q gd
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V DD = 15 V,
V GS = 0 V to 4.5 V I D = 13 A
Q2:
V DD = 15 V,
I D = 17 A
Q1
Q2
Q1
Q2
Q1
Q2
9.5
12
3.9
4
2.6
2.5
13
17
nC
nC
nC
?2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
2
www.fairchildsemi.com
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