参数资料
型号: FDMS4435BZ
厂商: Fairchild Semiconductor
文件页数: 2/7页
文件大小: 0K
描述: MOSFET P-CH DUAL POWER56
标准包装: 3,000
系列: PowerTrench®
FET 型: MOSFET P 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V
电流 - 连续漏极(Id) @ 25° C: 9A
开态Rds(最大)@ Id, Vgs @ 25° C: 20 毫欧 @ 9A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 47nC @ 10V
输入电容 (Ciss) @ Vds: 2050pF @ 15V
功率 - 最大: 2.5W
安装类型: 表面贴装
封装/外壳: 8-PowerTDFN
供应商设备封装: Power56
包装: 带卷 (TR)
Electrical Characteristics T J = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
Δ BV DSS
Δ T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 μ A, V GS = 0 V
I D = -250 μ A, referenced to 25 °C
V DS = -24 V, V GS = 0 V
V GS = ±25 V, V DS = 0 V
-30
-23
-1
±10
V
mV/°C
μ A
μ A
On Characteristics
V GS(th)
Δ V GS(th)
Δ T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 μ A
I D = -250 μ A, referenced to 25 °C
-1.0
-1.9
6
-3.0
V
mV/°C
V GS = -10 V, I D = -9.0 A
15
20
r DS(on)
g FS
Static Drain to Source On Resistance
Forward Transconductance
V GS = -4.5 V, I D = -6.5 A
V GS = -10 V, I D = -9.0 A
T J = 125 °C
V DS = -5 V, I D = -9.0 A
22
21
25
37
28
m Ω
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = -15 V, V GS = 0 V,
f = 1 MHz
1540
290
260
5
2050
390
385
pF
pF
pF
Ω
Switching Characteristics
t d(on)
Turn-On Delay Time
9
17
ns
t r
t d(off)
t f
Q g
Q g
Q gs
Q gd
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V DD = -15 V, I D = -9.0 A,
V GS = -10 V, R GEN = 6 Ω
V GS = 0 V to -10 V
V GS = 0 V to -4.5 V V DD = -15 V,
I D = -9.0 A
10
35
19
34
18
5
9
18
56
33
47
25
ns
ns
ns
nC
nC
nC
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0 V, I S = -1.9 A
V GS = 0 V, I S = -9.0 A
(Note 2)
(Note 2)
0.75
0.86
1.2
1.5
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = -9.0 A, di/dt = 100 A/ μ s
25
12
39
21
ns
nC
Notes :
1. R θ JA is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R θ JC is guaranteed by design while R θ CA is determined by
the user's board design.
a) 50 °C/W when mounted on a
1 in 2 pad of 2 oz copper
b) 125 °C/W when mounted
on a minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3. E AS of 18 mJ is based on starting T J = 25 ° C, L = 1 mH, I AS = -6 A, V DD = -27 V, V GS = -10 V. 100% tested at L = 0.3 mH, I AS = -8 A.
4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
?2011 Fairchild Semiconductor Corporation
FDMS4435BZ Rev.C3
2
www.fairchildsemi.com
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