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| 型号： | FDS3890 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/5页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH DUAL 80V 4.7A SO-8 |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品变化通告： | Mold Compound Change 12/Dec/2007 |
| 产品目录绘图： | Power MOSFET, 8-SOP, SO-8 |
| 标准包装： | 1 |
| 系列： | PowerTrench® |
| FET 型： | 2 个 N 沟道（双） |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 80V |
| 电流 - 连续漏极(Id) @ 25° C： | 4.7A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 44 毫欧 @ 4.7A，10V |
| Id 时的 Vgs(th)（最大）： | 4V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 35nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 1180pF @ 40V |
| 功率 - 最大： | 900mW |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | SO-8 |
| 包装： | 标准包装 |
| 产品目录页面： | 1604 (CN2011-ZH PDF) |
| 其它名称： | FDS3890DKR |
Electrical Characteristics
T A = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
Drain-Source Avalanche Ratings (Note 2)
W DSS
Single Pulse Drain-Source
V DD = 40 V, I D = 4.7 A
175
mJ
Avalanche Energy
I AR
Maximum Drain-Source Avalanche
4.7
A
Current
Off Characteristics
BV DSS
? BV DSS
? T J
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
V GS = 0 V, I D = 250 μ A
I D = 250 μ A, Referenced to 25 ° C
80
86
V
mV/ ° C
I DSS
I GSSF
I GSSR
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
V DS = 64 V,
V GS = 20 V,
V GS = –20 V
V GS = 0 V
V DS = 0 V
V DS = 0 V
1
100
–100
μ A
nA
nA
On Characteristics
(Note 2)
V GS(th)
? V GS(th)
? T J
R DS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
V DS = V GS , I D = 250 μ A
I D = 250 μ A, Referenced to 25 ° C
V GS = 10 V, I D = 4.7 A
2
2.3
–6
34
4
44
V
mV/ ° C
m ?
On–Resistance
V GS = 6.0 V, I D = 4.4 A
V GS = 10 V, I D = 4.7 A, T J = 125 ° C
37
60
50
82
I D(on)
g FS
On–State Drain Current
Forward Transconductance
V GS = 10 V,
V DS = 10 V,
V DS = 5 V
I D = 4.7 A
20
24
A
S
Dynamic Characteristics
C iss
C oss
C rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V DS = 40 V,
f = 1.0 MHz
V GS = 0 V,
1180
171
50
pF
pF
pF
Switching Characteristics
(Note 2)
t d(on)
t r
t d(off)
t f
Q g
Q gs
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
V DD =40 V,
V GS = 10 V,
V DS = 40 V,
V GS = 10 V
I D = 1 A,
R GEN = 6 ?
I D = 4.7 A,
11
8
26
12
25
4.5
20
16
50
25
35
ns
ns
ns
ns
nC
nC
Q gd
Gate–Drain Charge
5.8
nC
Drain–Source Diode Characteristics and Maximum Ratings
I S
Maximum Continuous Drain–Source Diode Forward Current
1.3
A
V SD
Drain–Source Diode Forward
Voltage
V GS = 0 V, I S = 1.3 A
(Note 2)
0.74
1.2
V
Notes:
1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user's board design.
a) 78°C/W when
mounted on a 1in 2
pad of 2 oz copper
b) 125°C/W when
mounted on a .04 in 2
pad of 2 oz copper
c) 135°C/W when mounted on a
minimum pad.
2. Pulse Test: Pulse Width < 300 μ s, Duty Cycle < 2.0%
FDS3890 Rev B(W)
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