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参数资料
型号： FDS4435BZ_F085
厂商： Fairchild Semiconductor
文件页数： 2/6页
文件大小： 0K
描述： MOSFET P-CH 30V 8-SOIC
标准包装： 2,500
系列： PowerTrench®
FET 型： MOSFET P 通道，金属氧化物
FET 特点： 逻辑电平门
漏极至源极电压(Vdss)： 30V
电流 - 连续漏极(Id) @ 25° C： 8.8A
开态Rds（最大）@ Id, Vgs @ 25° C： 20 毫欧 @ 8.8A，10V
Id 时的 Vgs(th)（最大）： 3V @ 250µA
闸电荷(Qg) @ Vgs： 40nC @ 10V
输入电容 (Ciss) @ Vds： 1845pF @ 15V
功率 - 最大： 1W
安装类型： 表面贴装
封装/外壳： 8-SOIC（0.154"，3.90mm 宽）
供应商设备封装： 8-SOICN
包装： 带卷 (TR)
Electrical Characteristics T J = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV DSS
' BV DS S
' T J
I DSS
I GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I D = -250 P A, V GS = 0V
I D = -250 P A, referenced to 25°C
V DS = -24V, V GS = 0V
V GS = ±25V, V DS = 0V
-30
-21
1
±10
V
mV/ °C
P A
P A
On Characteristics
V GS(th)
' V GS(th )
' T J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V GS = V DS , I D = -250 P A
I D = -250 P A, referenced to 25°C
-1
-2.1
6
-3
V
mV/°C
V GS = -10V, I D = -8.8A
16
20
r DS(on)
Static Drain to Source On Resistance
V GS = -4.5V, I D = -6.7A
26
35
m :
V GS = -10V, I D = -8.8A, T J = 125°C
22
28
g FS
Forward Transconductance
V DS = -5V, I D = -8.8A
24
S
Dynamic Characteristics
C iss
C oss
C rss
R g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
V DS = -15V, V GS = 0V,
f = 1MHz
f = 1MHz
1385
275
230
4.5
1845
365
345
pF
pF
pF
:
Switching Characteristics
t d(on)
t r
t d(off)
t f
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
V DD = -15V, I D = -8.8A,
V GS = -10V, R GEN = 6 :
10
6
30
12
20
12
48
22
ns
ns
ns
ns
Q g
Q g
Q gs
Total Gate Charge
Total Gate Charge
Gate to Source Charge
V GS = 0V to -10V
V GS = 0V to -5V
V DD = -15V,
I D = -8.8A
28
16
5.2
40
23
nC
nC
nC
Q gd
Gate to Drain “Miller” Charge
7.4
nC
Drain-Source Diode Characteristics
V SD
Source to Drain Diode Forward Voltage
V GS = 0V, I S = -8.8A
(Note 2)
-0.9
-1.2
V
t rr
Q rr
Reverse Recovery Time
Reverse Recovery Charge
I F = -8.8A, di/dt = 100A/ P s
29
23
44
35
ns
nC
NOTES:
1. R T JA is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R T JC is guaranteed by design while R T CA is determined by
the user's board design.
a. 50°C/W when mounted on
a 1 in 2 pad of 2 oz copper.
b. 125°C/W when mounted on
a minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 30 0 P s, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
4. Starting T J = 25°C, L = 1mH, I AS = -7A, V DD = -30V, V GS = -10V
?2009 Fairchild Semiconductor Corporation
FDS4435BZ _F085 Rev. A
2
www.fairchildsemi.com
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