参数资料
型号: FMS6502MTC24
厂商: Fairchild Semiconductor
文件页数: 12/13页
文件大小: 0K
描述: IC VIDEO SWITCH 8IN/6OUT 24TSSOP
标准包装: 61
功能: 视频交叉点开关
电路: 1 x 8:6
电压电源: 单电源
电压 - 电源,单路/双路(±): 3.135 V ~ 5.25 V
电流 - 电源: 55mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 管件
FMS6502
8-Input,
6-Output
V
ideo
Switch
Matrix
with
Output
Drivers,
Input
Cl
amp,
and
Bias
Circuitry
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6502 Rev. 1.0.0
8
Figure 6.
Acknowledgement on the I2C Bus
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is unlim-
ited. Each byte of eight bits is followed by an acknowl-
edge bit. The acknowledge bit is a HIGH level signal put
on the bus by the transmitter while the master generates
an extra acknowledge-related clock pulse. The slave
receiver addressed must generate an acknowledge after
the reception of each byte. A master receiver must gen-
erate an acknowledge after the reception of each byte
clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse so the SDA line
is stable LOW during the HIGH period of the acknowl-
edge-related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte clocked out of the slave. In
this event, the transmitter must leave the data line HIGH
to enable the master to generate a stop condition.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
START
condition
12
89
clock pulse for
acknowledgement
I2C Bus Protocol
Before any data is transmitted on the I2C bus, the device
which is to respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C bus configuration for a data
write to the FMS6502 is shown in Figure 7.
Figure 7. Write Register Address to Pointer Register; Write Data to Selected Register
3.3V Operation
The FMS6502 operates from a single 3.3V supply. With
Vcc = 3.3V, the digital input low (Vil) is 0V to 1V and the
digital input high (Vih) is 1.8V to 2.9V.
A6
A5
A4
A3
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
1
ACK. BY
FMS6502
ACK. BY
FMS6502
FRAME1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
FMS6502
FRAME 3
DATA BYTE
SCL
SDA
START BY
MASTER
STOP BY
MASTER
SCL(CONTINUED)
SDA(CONTINUED)
9
1
9
1
9
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