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参数资料
| 型号： | FMS6502MTC24 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO SWITCH 8IN/6OUT 24TSSOP |
| 标准包装： | 61 |
| 功能： | 视频交叉点开关 |
| 电路： | 1 x 8:6 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3.135 V ~ 5.25 V |
| 电流 - 电源： | 55mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
FMS6502
8-Input,
6-Output
V
ideo
Switch
Matrix
with
Output
Drivers,
Input
Cl
amp,
and
Bias
Circuitry
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6502 Rev. 1.0.0
4
Digital Interface
The I2C-compatibe interface is used to program output
enables, input-to-output routing, and input bias configu-
ration. The I2C address of the FMS6502 is 0x06 (0000
0110) with the ability to offset based upon the values of
the ADDR0 and ADDR1 inputs. Offset addresses are
defined below:
Data and address data of eight bits each are written to
the FMS6502 I2C address register to access control
functions.
For efficiency, a single data register is shared between
two outputs for input selection. More than one output can
select the same input channel for one-to-many routing.
The clamp / bias control bits are written to their own
internal address since they should remain the same
regardless of signal routing. They are set based on the
input signal that is connected to the FMS6502.
All undefined addresses may be written without effect.
Output Control Register Contents and Defaults
Output Control Register MAP
Clamp Control Register Contents and Defaults
Clamp Control Register Map
Gain Control Register Contents and Defaults
Gain Control Register Map
Note:
1. When the OFF input selection is used, the output amplifier is powered down and enters a high-impedance state.
ADDR1
ADDR0
Binary
Hex
0
0000 0110
0x06
0
1
0100 0110
0x46
1
0
1000 0110
0x86
1
1100 0110
0xC6
Control Name
Width
Type
Default
Bit(s)
Description
In-A
4 bits
Write
0
3:0
Input selected to drive this output:
0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8
In-B
4 bits
Write
0
7:4
Input selected to drive this output:
0000=OFF1, 0001=IN1, 0010=IN2, 1000=IN8
Name
Address
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
OUT1,2
0x00
B3-Out2
B2-Out2
B1-Out2
B0-Out2
B3-Out1
B2-Out1
B1-Out1
B0-Out1
OUT3,4
0x01
B3-Out4
B2-Out4
B1-Out4
B0-Out4
B3-Out3
B2-Out3
B1-Out3
B0-Out3
OUT5,6
0x02
B3-Out6
B2-Out6
B1-Out6
B0-Out6
B3-Out5
B2-Out5
B1-Out5
B0-Out5
Control Name
Width
Type
Default
Bit(s)
Description
Clmp
1 bit
Write
0
7:0
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Name
Address
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CLAMP
0x03
Clmp8
Clmp7
Clmp6
Clmp5
Clmp4
Clmp3
Clmp2
Clmp1
Control Name
Width
Type
Default
Bit(s)
Description
Gain
1 bit
Write
0
7:0
Output Gain selection: 0 = 6dB, 1 = 0dB
Name
Address
Bit 7
Bit 6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
GAIN
0x04
Unused
Gain6
Gain5
Gain4
Gain3
Gain2
Gain1
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