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| 型号： | FR3-1M |
| 厂商： | TechTools |
| 文件页数： | 25/38页 |
| 文件大小： | 0K |
| 描述： | EMULATOR FLASH FLEXROM III 1MEG |
| 标准包装： | 1 |
| 系列： | FlexROM™ III |
| 类型： | 存储器 |
| 适用于相关产品： | 外部 FLASH、EPROM 或 SRAM 设备 |
| 所含物品： | 需要 FR3 FlexROM III 仿真器、缆线（菊花链、LPT、迷你型夹和目标）、软件、有源缆线模块 |
| 其它名称： | FR31M |
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Filtering
FlexROM III provides the ability to filter noise out of the target’s control signals before using them to
control the SRAMs or to detect the end of valid cycles (for arbitration, snap-shot & trigger). Any noise on a
control signal while it is active can corrupt a target write or cut into the read margins. Filtering out this
noise greatly improves emulator performance in noisy environments.
The up side to filtering is a more robust emulator. The trade-off (there’s ALWAYS a trade-off) is that the
greater the filtering, the longer it takes to determine that the cycle really ended. For example, if we are
filtering out pulses shorter than 20ns, the true end of cycle must obviously last somewhat longer than 20ns
or we will filter it out as noise. Even if end-of-cycle gets filtered out, the target can usually continue to
function properly. The end-of-cycle detection is used to update our SNAP-SHOT register, the trigger
circuit and to terminate target write cycles.
The default settings enable the control line filters and sets them to minimum filtering. This is a reasonable
default that allows full speed access on most targets. In fact, most targets could increase the filtering to
MAX and still meet timing.
The only time you may have to turn off filtering is if:
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The target does writes to the emulator OR you are doing READY mode arbitrated accesses.
AND the target has very short cycle recovery times
AND the target has fast access time (45ns) requirements
If you are not doing arbitrated accesses to the emulator and the target does not write to the emulator, you
can usually add as much filtering as you want. In this situation, too much filtering on a target with short
recovery times would result in the SNAP-SHOT & trigger circuits failing to update, but the target would
function correctly as long the LATCHING options (see next section) are left at their defaults.
Latching
FlexROM III always latches the address lines during a target write. This enables it to enforce proper
address hold times to the SRAM despite varying path delays or sloppy target timing. By default, they are
only held stable while the target CS and WT signals are BOTH active.
In some cases, it might be desirable to latch the addresses on reads as well as writes or to latch them as soon
as CS goes active. To avoid latching noise, it is sometimes desirable to delay latching until some time after
the control signal. Most system noise occurs immediately after control signal transitions. Delaying the
actual freezing allows the signals to settle.
FlexROM III gives you the ability to select the source that triggers the latch and how long AFTER the
trigger it will wait before actually freezing the signals.
The latching options and possible reasons you would want to use them are listed below.
FlexROM III User’s Manual
23
Copyright ? 2001, TechTools
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