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| 型号： | FS6370-01G-XTD |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3-PLL EEPROM 16SOIC |
| 标准包装： | 48 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1115 (CN2011-ZH PDF) |
| 其它名称： | 766-1025 |
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FS6370
Table 13: AC Timing Specifications (Continued)
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Clock Output (PLL C clock via CLK_C pin)
Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs
active
100
45
Jitter, Long Term (
σ
y(τ))*
Tj(LT)
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs
active (A=50MHz, B=60MHz, D=14.318MHz)
40
105
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active
100
120
Jitter, Period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active
(A=50MHz, B=60MHz, D=14.318MHz)
40
440
ps
Clock Output (Crystal Oscillator via CLK_D pin)
Duty Cycle*
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
14.318
45
55
%
On rising edges 500s apart at 2.5V relative to an ideal clock,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs
active
14.318
20
Jitter, Long Term (
σ
y(τ))*
Tj(LT)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz,
C=40MHz)
14.318
40
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, no other PLLs active
14.318
90
Jitter, Period (peak-peak)*
tj(ΔP)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz,
C=40MHz)
14.318
450
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
Table 14: Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Min.
Max.
Units
Clock frequency
fSCL
SCL
0
100
kHz
Bus free time between STOP and START
tBUF
4.7
μs
Set up time, START (repeated)
tsu:STA
4.7
μs
Hold time, START
thd:STA
4.0
μs
Set up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
μs
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
3.5
μs
Rise time, data and clock
tR
SDA, SCL
1000
ns
Fall time, data and clock
tF
SDA, SCL
300
ns
High time, clock
tHI
SCL
4.0
μs
Low time, clock
tLO
SCL
4.7
μs
Set up time, STOP
tsu:STO
4.0
μs
Rev. 3 | Page 22 of 28 | www.onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FS6370-01G-XTP | 功能描述:时钟发生器及支持产品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| FS6377 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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