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参数资料
| 型号： | FS6370-01G-XTD |
| 厂商： | ON Semiconductor |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3-PLL EEPROM 16SOIC |
| 标准包装： | 48 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1115 (CN2011-ZH PDF) |
| 其它名称： | 766-1025 |
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FS6370
achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values
comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and
acquisition time.
To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded
with the dual-modulus pre-scaler. The A-counter controls the modulus of the pres-caler. If the value programmed into the A-counter is
A, the pre-scaler will be set to divide by N+1 for A pre-scaler outputs. Thereafter, the prescaler divides by N until the M-counter output
resets the A-counter, and the cycle begins again. Note that N=8, and A and M are binary numbers.
Figure 4: Feedback Divider
Suppose that the A-counter is programmed to zero. The modulus of the pre-scaler will always be fixed at N; and the entire modulus of
the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the pre-scaler to switch to a divide-by-N+1 for its first divide
cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the
feedback divider. The overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.
3.1.3. Feedback Divider Programming
For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-
counter. Therefore, not all divider moduli below 56 are available for use. This is shown in Table 2.
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
A-Counter: FBKDIV[2:0]
M-Counter:
FBKDIV[10:3]
000
001
010
011
100
101
110
111
00000001
8
9
-
00000010
16
17
18
-
00000011
24
25
26
27
-
00000100
32
33
34
35
36
-
00000101
40
41
42
43
44
45
-
00000110
48
49
50
51
52
53
54
-
00000111
56
57
58
59
60
61
62
63
Feedback Divider Modulus
3.2 Post Divider Muxes
As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference
frequency. The mux selection is controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers (muxes C and D in Figure 2) can be altered without reprogramming by a logic-level
input on the SEL_CD pin.
Rev. 3 | Page 4 of 28 | www.onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FS6370-01G-XTP | 功能描述:时钟发生器及支持产品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| FS6377 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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