参数资料
型号: FS6370-01G-XTD
厂商: ON Semiconductor
文件页数: 24/28页
文件大小: 0K
描述: IC CLOCK GEN 3-PLL EEPROM 16SOIC
标准包装: 48
类型: PLL 时钟发生器
PLL:
输入: 晶体
输出: CMOS
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 无/无
频率 - 最大: 230MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 5.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 管件
产品目录页面: 1115 (CN2011-ZH PDF)
其它名称: 766-1025
FS6370
3.3 Post Dividers
A post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the
variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to:
where NP is the post divider modulus. The extra integer in the denominator permits more flexibility in the programming of the loop for
many applications where frequencies must be achieved exactly.
The modulus on two of the four post dividers (post dividers C and D in Figure 2) can be altered without reprogramming by a logic level
on the SEL_CD pin.
4.0 Device Operation
The FS6370 has two modes of operation:
Program mode: during which either the EEPROM or the FS6370 control registers can be programmed directly with the desired PLL
settings
Run mode: where the PLL settings stored the EEPROM are transferred to the FS6370 control registers on power-up, and the device
then operates based on those settings
Note that the EEPROM locations are not physically the same registers used to control the FS6370.
Direct access to either the EEPROM or the FS6370 control registers is achieved in program mode. The EEPROM register contents are
automatically transferred to the FS6370 control registers in normal device operation (run mode).
4.1 MODE Pin
The MODE pin controls the mode of operation. A logic-low places the FS6370 in program mode. A logic-high puts the device in run
mode. A pull-up on this pin defaults the device into run mode.
Reprogramming of either the control registers or the EEPROM is permitted at any time if the MODE pin is a logic-low.
Note, however, that a logic-high state on the MODE pin is latched so that only one transfer of EEPROM data to the FS6370 control
registers can occur. If a second transfer of EEPROM data into the FS6370 is desired, power (VDD) must be removed and reapplied to
the device.
The MODE pin also controls the function of the PD/SCL and OE/SDA pins. In run mode, these two pins function as power-down (PD)
and output enable (OE) controls. In program mode, the pins function as the I2C interface for clock (SCL) and data (SDA).
4.2 SEL_CD Pin
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D, and post dividers C and D without having to
reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on
the SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-
divider(s) is/are altered.
4.3 Oscillator Overdrive
For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be
connected to XOUT and XIN must be left unconnected (float).
Rev. 3 | Page 5 of 28 | www.onsemi.com
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FS6370-01G-XTP 功能描述:时钟发生器及支持产品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
FS6377 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56