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参数资料
| 型号： | FS6370-01G-XTD |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 3-PLL EEPROM 16SOIC |
| 标准包装： | 48 |
| 类型： | PLL 时钟发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 230MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1115 (CN2011-ZH PDF) |
| 其它名称： | 766-1025 |
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FS6370
9.0 Programming Information
Table 3: Register Map (Note: All register bits are cleared to zero on power-up)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 15
MUX_D2[1:0]
(selected via SEL_CD = 1)
MUX_C2[1:0]
(selected via SEL_CD = 1)
PDPOST_D
PDPOST_C
PDPOST_B
PDPOST_A
Byte 14
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
Byte 13
POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
Byte 12
POST_B[3:0]
POST_A[3:0]
Byte 11
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
LFTC_C2
(SEL_CD=1)
CP_C2
(SEL_CD=1)
FBKDIV_C2[10:8] M-Counter
(selected via SEL_CD pin = 1)
Byte 10
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
Byte 9
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
Byte 8
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
(SEL_CD=0)
CP_C1
(SEL_CD=0)
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD = 0)
Byte 7
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
Byte 6
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
Byte 5
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
Byte 4
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
Byte 3
REFDIV_B[7:0]
Byte 2
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
Byte 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
Byte 0
REFDIV_A[7:0]
9.1 Control Bit Assignments
If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output
frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time
constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
9.1.1. Power-Down
All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the
PD input is asserted. If the power-down bit contains a one, the related circuit will shut down if the PD pin is high (run mode only). When
the PD pin is low, power is enabled to all circuits.
If the power-down bit contains a zero, the related circuit will continue to function regardless of the PD pin state.
Rev. 3 | Page 12 of 28 | www.onsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FS6370-01G-XTP | 功能描述:时钟发生器及支持产品 EE PROG 3-PLL CLOCK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| FS6377 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01 | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G | 制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC |
| FS6377-01G-XTD | 功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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