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FS6370

Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write

procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a

logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit

word. The master does not acknowledge the transfer but does generate a STOP condition.

8.2.4. Sequential Register Write Procedure

Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after

each write. This procedure is more efficient than the random register write if several registers must be written.

To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the

addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address

is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to 16 bytes of data

into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device

between each byte of data must occur before the next data byte is sent.

Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP

condition to occur. Registers are therefore updated at different times during a sequential register write.

8.2.5. Sequential Register Read Procedure

Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by

one after each read. This procedure is more efficient than the random register read if several registers must be read.

To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure.

This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address.

The register address is then written into the slave's address pointer.

Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write

procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a

logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all 16 bytes

of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than

zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.

Rev. 3 | Page 10 of 28 | www.onsemi.com

相关代理商/技术参数	参数描述
FS6370-01G-XTP	功能描述:时钟发生器及支持产品 EE PROG 3-PLL CLOCK RoHS:否制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
FS6377	制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01	制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G	制造商:AMI 制造商全称:AMI 功能描述:Programmable 3-PLL Clock Generator IC
FS6377-01G-XTD	功能描述:时钟发生器及支持产品 I2C PROG 3-PLL CLK RoHS:否制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56

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