参数资料
型号: FT2232D-REEL
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 31/61页
文件大小: 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
产品培训模块: USB Introduction
标准包装: 1
系列: USBmadeEZ-FIFO,FT-X,X-Chip
特点: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道数: 2,DUART
FIFO's: 384 字节
规程: RS232,RS422,RS485
电源电压: 4.35 V ~ 5.25 V
带并行端口:
带自动流量控制功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP
包装: 标准包装
产品目录页面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名称: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
37
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
8.2 245 FIFO Interface Mode Signal Descriptions and Interface
Configurations
When either Channel A or Channel B is in 245 FIFO mode, the IO signal lines are configured as follows:-
Pin#
Signal
Type
Description
Channel A
Channel B
24
40
D0
I/O
FIFO Data Bus Bit 0
23
39
D1
I/O
FIFO Data Bus Bit 1
22
38
D2
I/O
FIFO Data Bus Bit 2
21
37
D3
I/O
FIFO Data Bus Bit 3
20
36
D4
I/O
FIFO Data Bus Bit 4
19
35
D5
I/O
FIFO Data Bus Bit 5
17
33
D6
I/O
FIFO Data Bus Bit 6
16
32
D7
I/O
FIFO Data Bus Bit 7
Table 8.2 FIFO Data Bus Group **Note 17
Pin#
Signal
Type
Description
Channel A
Channel B
15
30
RXF#
OUTPUT
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low then high again ** Note 18
13
29
TXE#
OUTPUT
When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high
then low. ** Note 18
12
28
RD#
INPUT
Enables Current FIFO Data Byte on D0..D7 when low.
Fetches the next FIFO Data Byte (if available) from the
Receive FIFO Buffer when RD# goes from low to high.
** Note 17
11
27
WR
INPUT
Writes the Data Byte on the D0..D7 into the Transmit
FIFO Buffer when WR goes from high to low.
** Note 17
10
26
SI/WU
INPUT
The Send Immediate / WakeUp signal combines two
functions on a single pin. If USB is in suspend mode
(PWREN# = 1) and remote wakeup is enabled in the
EEPROM, strobing this pin low will cause the device to
request a resume on the USB Bus. Normally, this can be
used to wake up the Host PC.
During normal operation (PWREN# = 0), if this pin is
strobed low any data in the device TX buffer will be sent
out over USB on the next Bulk-IN request from the
drivers regardless of the pending packet size. This can
be used to optimise USB transfer speed for some
applications. Tie this pin to VCCIO if not used.
Table 8.3 FIFO Control Interface Group
**Note 17: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be
programmed to gently pull low during USB suspend (PWREN# = “1” ) by setting this option in the
EEPROM.
**Note 18: During device reset, these pins are tri-state but pulled up to VCCIO via internal 200K
resistors.
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