参数资料
型号: FT2232D-REEL
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 40/61页
文件大小: 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
产品培训模块: USB Introduction
标准包装: 1
系列: USBmadeEZ-FIFO,FT-X,X-Chip
特点: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道数: 2,DUART
FIFO's: 384 字节
规程: RS232,RS422,RS485
电源电压: 4.35 V ~ 5.25 V
带并行端口:
带自动流量控制功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP
包装: 标准包装
产品目录页面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名称: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
45
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
**Note 28: In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
**Note 29: These instructions are fully described in the application note AN2232L-01 - “Command Processor For
MPSSE and MCU Host Bus Emulation Modes”.
Figure 8.10 MCU Host Bus Emulation Mode Signal Timing - Write Cycle
Time
Description
t1
High address byte is placed on the bus if the extended write is used.
t2
Low address byte is put out.
t3
1 clock period for address is set up.
t4
ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is
low.
t5
ALE goes low to latch address and CS# is set active low.
t6
Data driven onto the bus.
t7
1 clock period for data setup.
t8
WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.
t9
WR# is driven inactive high.
t10
CS# is driven inactive, 1/2 a clock period after WR# goes inactive
t11
Data is held until this point, and may now change
Table 8.11 MCU Host Bus Emulation Mode Signal Timing - Write Cycle
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