参数资料
型号: FT2232D-REEL
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 61/61页
文件大小: 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
产品培训模块: USB Introduction
标准包装: 1
系列: USBmadeEZ-FIFO,FT-X,X-Chip
特点: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道数: 2,DUART
FIFO's: 384 字节
规程: RS232,RS422,RS485
电源电压: 4.35 V ~ 5.25 V
带并行端口:
带自动流量控制功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP
包装: 标准包装
产品目录页面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名称: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
9
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Pin No.
Name
Type
Description
6
3V3OUT
OUTPUT
3.3 volt Output from the integrated L.D.O. regulator This pin should be
decoupled to GND using a 33nF ceramic capacitor in close proximity to
the device pin. Its prime purpose is to provide the internal 3.3V supply
to the USB transceiver cell and the RSTOUT# pin. A small amount of
current (<= 5mA) can be drawn from this pin to power external 3.3V
logic if required.
3, 42
VCC
PWR
+4.35 volt to +5.25 volt VCC to the device core, LDO and non-UART /
FIFO controller interface pins.
14
VCCIOA
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO A Channel interface pins
10..13, 15..17 and 19..24. When interfacing with 3.3V external logic in a
bus powered design connect VCCIO to a 3.3V supply generated from the
USB bus. When interfacing with 3.3V external logic in a self powered
design connect VCCIO to the 3.3V supply of the external logic.
Otherwise connect to VCC to drive out at 5V CMOS level.
31
VCCIOB
PWR
+3.0 volt to +5.25 volt VCC to the UART / FIFO B Channel interface pins
26..30, 32..33 and 35..40. When interfacing with 3.3V external logic in a
bus powered design connect VCCIO to a 3.3V supply generated from the
USB bus. When interfacing with 3.3V external logic in a self powered
design connect VCCIO to the 3.3V supply of the external logic.
Otherwise connect to VCC to drive out at 5V CMOS level.
9,18,
25, 34
GND
PWR
Device - Ground Supply Pins
46
AVCC
PWR
Device - Analog Power Supply for the internal x8 clock multiplier. A low
pass filter consisting of a 470 Ohm series resistor and a 100 nF to GND
should be used on the supply to this pin.
45
AGND
PWR
Device - Analog Ground Supply for the internal x8 clock multiplier
Table 3.4.4 Power and Ground Group
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