参数资料
型号: FT2232D-REEL
厂商: FTDI, Future Technology Devices International Ltd
文件页数: 41/61页
文件大小: 0K
描述: IC USB FS DUAL UART/FIFO 48-LQFP
产品培训模块: USB Introduction
标准包装: 1
系列: USBmadeEZ-FIFO,FT-X,X-Chip
特点: USB 至 UART 和(或)FIFO、SPI、I2C、JTAG
通道数: 2,DUART
FIFO's: 384 字节
规程: RS232,RS422,RS485
电源电压: 4.35 V ~ 5.25 V
带并行端口:
带自动流量控制功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP
包装: 标准包装
产品目录页面: 634 (CN2011-ZH PDF)
配用: 768-1030-ND - MOD USB HS FT2232H EVAL
813-1009-ND - MODULE USB-TO-FPGA TOOL W/MANUAL
813-1001-ND - MODULE USB ADAPTR FOR FT2232D LP
813-1000-ND - MODULE USB ADAPTER FOR FT2232D
其它名称: 768-1010-6
Copyright 2010 Future Technology Devices International Limited
46
Document No.: FT_000173
FT2232D DUAL USB TO SERIAL UART
/FIFO IC Datasheet
Version 2.05
Clearance No.: FTDI# 127
Figure 8.11 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Time
Description
t1
High address byte is placed on the bus if the extended read is used -
otherwise t1 will not occur.
t2
Low address byte is put out.
t3
1 clock period for address set up.
t4
ALE goes high to enable address latch. This will extend to 2 clocks wide if
IORDY is low.
t5
ALE goes low to latch address, and CS# is set active low. This will extend to 3
clocks if IORDY is sampled low. CS# will always drop 1 clock after ALE has
gone high no matter the state of IORDY.
t6
Data is set as input (Hi-Z), and RD# is driven active low.
t7
1 clock period for data setup. This will extend to 5 clocks wide if IORDY# is
sampled low.
t8
RD# is driven inactive high.
t9
CS# is driven inactive 1/2 a clock period after RD# goes inactive, and the
data bus is set back to output.
Table 8.12 MCU Host Bus Emulation Mode Signal Timing - Read Cycle
Figure 8.12 MCU Host Bus Emulation Mode Signal Timing - Clock (OSC) Signal
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