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参数资料
| 型号： | FT245RQ-REEL |
| 厂商： | FTDI, Future Technology Devices International Ltd |
| 文件页数： | 8/37页 |
| 文件大小： | 0K |
| 描述： | IC USB TO PARALLEL FIFO 32-QFN |
| 产品培训模块： | USB Introduction |
| 标准包装： | 1 |
| 应用： | USB 至 FIFO 控制器 |
| 接口： | USB，FIFO，（同步/异步） |
| 电源电压： | 1.8 V ~ 5.25 V |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 634 (CN2011-ZH PDF) |
| 配用： | 768-1020-ND - MOD USB PARALLEL FIFO DEV FT245R |
| 其它名称： | 768-1012-6 |
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Copyright 2010 Future Technology Devices International Limited
16
Document No.: FT_000052
FT245R USB FIFO IC Datasheet Version 2.12
Clearance No.: FTDI# 39
4.2 Functional Block Descriptions
The following paragraphs detail each function within the FT245R. Please refer to the block
diagram shown in Figure 2.1.
Internal EEPROM. The internal EEPROM in the FT245R is used to store USB Vendor ID (VID), Product ID
(PID), device serial number, product description string and various other USB configuration descriptors.
The FT245R is supplied with the internal EEPROM pre-programmed as described in Section 9. A user area
of the internal EEPROM is available to system designers to allow storing additional data. The internal
EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement.
It can be programmed using the FTDI utility software called MPROG and FT_PROG, which can be
downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com).
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the
USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the
3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on
USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells
rather than to power external logic. However, it can be used to supply external circuitry requiring a
+3.3V nominal supply with a maximum current of 50mA.
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB
reset detection conditions respectfully. This function also incorporates the internal USB series termination
resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock
and data signals for the Serial Interface Engine (SIE) block.
Internal 12MHz Oscillator. The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This
provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference
clock for the SIE, USB Protocol Engine and FIFO controller blocks.
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal
Oscillator function and generates the 48MHz. The 48Mz clock reference is used by the USB DPLL and the
Baud Rate Generator blocks.
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data
stream.
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control
endpoint. It handles the low level USB protocol requests generated by the USB host controller and the
commands for controlling the functional parameters of the FIFO in accordance with the USB 2.0
specification Section 10.
FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the FIFO via the USB data OUT
endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents
of the FIFO using the RD# pin. (Rx relative to the USB interface).
FIFO TX Buffer (256 bytes). Data written into the FIFO using the WR pin is stored in the FIFO TX
(transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB
request for data from the device data IN endpoint. (Tx relative to the USB interface).
FIFO Controller with Programmable High Drive. The FIFO Controller handles the transfer of data
between the FIFO RX, the FIFO TX buffers and the external FIFO interface pins (D0 - D7).
Additionally, the FIFO signals have a configurable high drive strength capability which is configurable in
the EEPROM.
RESET Generator. The integrated Reset Generator Cell provides a reliable power-on reset to the device
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT245R.
RESET# can be tied to VCC or left unconnected if not being used.
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相关代理商/技术参数 |
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|---|---|
| FT245RQ-TRAY | 制造商:Future Technology Devices International (FTDI Chip) 功能描述:Single Chip USB Tray |
| FT24B3 031175 | 制造商:Comair Rotron 功能描述:FAN 120X120X25MM 24VDC |
| FT24B3-E2 | 制造商:Comair Rotron 功能描述:FAN FLIGHT II 120X120X25MM 24V |
| FT24B3-E2 | 制造商:Comair Rotron 功能描述:FAN FLIGHT II 120X120X25 24V |
| FT24C02A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Two-Wire Serial EEPROM |
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