- 您现在的位置：买卖IC网 > PDF目录223865 > GS81302QT07E-333 (GSI TECHNOLOGY) 16M X 8 QDR SRAM, 0.45 ns, PBGA165 PDF资料下载
参数资料
| 型号： | GS81302QT07E-333 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 16M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 1/30页 |
| 文件大小： | 914K |
| 代理商： | GS81302QT07E-333 |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
GS81302QT07/10/19/37E-333/300/250/200
144Mb SigmaQuad-II+TM
Burst of 2 SRAM
333 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.00 5/2011
1/30
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
2.0 clock Latency
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write controls sampled at data-in time
Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
Data Valid Pin (QVLD) Support
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
SigmaQuad Family Overview
The GS81302QT07/10/19/37E are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,994,944-bit (144Mb)
SRAMs. The GS81302QT07/10/19/37E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302QT07/10/19/37E SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Because Separate I/O SigmaQuad-II+ B2 RAMs always
transfer data in two packets, A0 is internally set to 0 for the
first read or write transfer, and automatically incremented by 1
for the next transfer. Because the LSB is tied off internally, the
address field of a SigmaQuad-II+ B2 RAM is always one
address pin less than the advertised index depth (e.g., the 8M x
18 has a 4M addressable index).
Parameter Synopsis
-333
-300
-250
-200
tKHKH
3.0 ns
3.3 ns
4.0 ns
5.0 ns
tKHQV
0.45 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
相关PDF资料 |
PDF描述 |
|---|---|
| GS81302TT07E-333IT | 16M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| GS81302TT07GE-333I | 16M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| GS816036AGT-250I | 512K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| GS8160E36GT-250 | 512K X 36 CACHE SRAM, 5.5 ns, PQFP100 |
| GS816118AGT-200IT | 1M X 18 CACHE SRAM, 6.5 ns, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| GS81302S18E-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.5NS 165FPBGA - Trays |
| GS81302S18E-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.5NS 165FPBGA - Trays |
| GS81302S18E-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
| GS81302S18E-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
| GS81302S18E-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。