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参数资料
| 型号： | GS81302QT07E-333 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 16M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 15/30页 |
| 文件大小： | 914K |
| 代理商： | GS81302QT07E-333 |
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GS81302QT07/10/19/37E-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
22/30
2011, GSI Technology
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
31 30 29
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
108
1
0
Control Signals
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
See BSDL Model
GSI Technology
JEDEC Vendor
ID Code
Pr
esence
Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
0
0 0 1 1 0 1 1 0 0 1
1
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| GS81302S18E-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.5NS 165FPBGA - Trays |
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| GS81302S18E-200I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
| GS81302S18E-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 144MBIT 8MX18 0.45NS 165FPBGA - Trays |
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