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参数资料
| 型号： | GS81302QT07E-333 |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 16M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件页数： | 8/30页 |
| 文件大小： | 914K |
| 代理商： | GS81302QT07E-333 |
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GS81302QT07/10/19/37E-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
16/30
2011, GSI Technology
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Max.
Units
Notes
Output High Voltage
VOH1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
1, 3
Output Low Voltage
VOL1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
2, 3
Output High Voltage
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
Output Low Voltage
VOL2
Vss
0.2
V
4, 6
Notes:
1.
IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2.
IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤350Ω).
3. Parameter tested with RQ = 250
Ω and VDDQ = 1.5 V
4. 0
Ω ≤ RQ ≤ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Operating Currents
Parameter
Symbol
Test Conditions
-333
-300
-250
-200
Notes
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating Current
(x36): DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time
≥ tKHKH Min
1440 mA
1450 mA
1330 mA
1340 mA
1130 mA
1140 mA
930 mA
940 mA
2, 3
Operating Current
(x18): DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time
≥ tKHKH Min
1265 mA
1275 mA
1250 mA
1260 mA
1060 mA
1070 mA
875 mA
885 mA
2, 3
Operating Current
(x9): DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time
≥ tKHKH Min
1265 mA
1275 mA
1250 mA
1260 mA
1060 mA
1070 mA
875 mA
885 mA
2, 3
Operating Current
(x8): DDR
IDD
VDD = Max, IOUT = 0 mA
Cycle Time
≥ tKHKH Min
1265 mA
1275 mA
1250 mA
1260 mA
1060 mA
1070 mA
875 mA
885 mA
2, 3
Standby Current
(NOP): DDR
ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs
≤ 0.2 V or ≥ VDD – 0.2 V
310 mA
320 mA
295 mA
305 mA
275 mA
285 mA
255 mA
265 mA
2, 4
Notes:
1.
Power measured with output pins floating.
2.
Minimum cycle, IOUT = 0 mA
3.
Operating current is calculated with 50% read cycles and 50% write cycles.
4.
Standby Current is only after all pending read and write burst operations are completed.
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