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参数资料
| 型号： | GS88237BD-200T |
| 厂商： | GSI TECHNOLOGY |
| 元件分类： | SRAM |
| 英文描述： | 256K X 36 CACHE SRAM, 2.7 ns, PBGA165 |
| 封装： | 13 X 15 MM, 1 MM PITCH, FBGA-165 |
| 文件页数： | 15/29页 |
| 文件大小： | 859K |
| 代理商： | GS88237BD-200T |
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GS88237BB/D-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 4/2008
22/29
2002, GSI Technology
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
DQ
VDDQ/2
50
Ω
30pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
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