参数资料
型号: GS88237BD-200T
厂商: GSI TECHNOLOGY
元件分类: SRAM
英文描述: 256K X 36 CACHE SRAM, 2.7 ns, PBGA165
封装: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件页数: 7/29页
文件大小: 859K
代理商: GS88237BD-200T
GS88237BB/D-333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 4/2008
15/29
2002, GSI Technology
Pipeline Mode Timing (+1)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
Begin
Read A
Cont
Deselect
Write B
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZ
tOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKH
Q(A)
D(B)
Q(C)
Q(C+1)
Q(C+2)
Q(C+3)
AB
C
Deselected with E1
E2 and E3 only sampled with ADSC
ADSC initiated read
CK
ADSP#
ADSC#
ADV#
Ao-An
GW#
BW#
Ba#-Bd#
E1#
E2
E3#
G#
DQa-DQd
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