29
Table 3.8
Pin Functions in Memory Mode (cont)
Pin No.
Abbre-
viation
REG
Compact
Flash
PC-ATA
Card
Input/
Output Function
44
61
Input
Input pin for switching between common and
attribute area access.
Drive high for common area access, and low for
attribute area access. As the attribute area section is
allocated to even addresses, D8–D15 are invalid in
word access mode. In byte access, odd addresses
are invalid.
BVD1
46
63
Output Originally intended to indicate the card’s internal
battery voltage level, but as this card has no battery,
the output of this pin is always high.
BVD2
45
62
Output Originally intended to indicate the card’s internal
battery voltage level, but as this card has no battery,
the output of this pin is always high.
RESET
41
58
Input
All registers in the card can be cleared by high-level
input at this pin. Initialization is then started, and
RDY/BSY output goes high.
WAIT
42
59
Output I/O access or memory access cycle execution is
kept waiting while the output of this pin is low.
INPACK
VS1
,
VS2
43
60
Output Not used in memory card mode.
33, 40
43, 57
Output These pins indicate the required input voltage value
for this card (CIS information).
3.4
I/O Mode (Primary/Secondary/Contiguous)
The card enters memory mode immediately after being powered on and in a hardware reset.
Therefore, in order to use the card in I/O mode, the configuration option register in the attribute
region must be set for the card as shown in tables 3.9 to 3.11.
In I/O mode, reading and writing is performed by controlling
IORD
and
IOWR
.
WE
and
OE
must
be held high.
This mode may be useful when using an MPU that has
IORD
and
IOWR
signals.
The pin interface in I/O mode is shown in tables 3.14 and 3.15. For the method of accessing the
registers, and timing details, see tables 3.9 to 3.13, etc.