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参数资料
| 型号： | HFA3860A |
| 厂商： | Intersil Corporation |
| 英文描述： | Direct Sequence Spread Spectrum Baseband |
| 中文描述： | 直接序列扩频基带 |
| 文件页数： | 14/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860A |
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2-144
The four fields for the header shown in Figure 9 are:
Signal Field (8 Bits).
This field indicates what data rate the
data packet that follows the header will be. The HFA3860A
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK or
B/QMBOK demodulation at the end of the always DBPSK
preamble and header fields.
Service Field (8 Bits)
- This field is currently unassigned
and can be utilized as required by the user. Set to 00h for
compliance with IEEE 802.11.
Length Field (16 Bits).
This field indicates the number of
microseconds it will take to transmit the payload data
(MPDU). The external controller will check the length field in
determining when it needs to de-assert the RX_PE.
CCITT - CRC 16 Field (16 Bits)
- This field includes the
16-bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The HFA3860A receiver will
indicate a CCITT - CRC 16 error via CR24 bit 2 and will
lower MD_RDY if there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x
16
+ x
12
+ x
5
+ 1
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 6 .
Defines the preamble length minus the SFD in symbols.
The 802.11 protocol requires a setting of 128d = 80h.
CR 15.
Defines the length of time that the demodulator
searches for the SFD before returning to acquisition.
CR 16.
The contents of this register define DBPSK
modulation. If CR 20 bits 1 and 0 are set to indicate DBPSK
modulation then the contents of this register are transmitted
in the signal field of the header.
CR 17.
The contents of this register define DQPSK
modulation. If CR 20 bits 1 and 0 are set to indicate DQPSK
modulation then the contents of this register are transmitted
in the signal field of the header.
CR 18.
The contents of this register define BMBOK
modulation. If CR 20 bits 1 and 0 are set to indicate BMBOK
modulation then the contents of this register are transmitted
in the signal field of the header.
CR 19.
The contents of this register define QMBOK
modulation. If CR 20 bits 1 and 0 are set to indicate QMBOK
modulation then the contents of this register are transmitted
in the signal field of the header.
CR 20.
The last two bits of the register indicate what
modulation is to be used for the data portion of the packet.
CR 21.
The value to be used in the Service field.
CR 22, 23.
Defines the value of the transmit data length field.
This value includes all symbols following the last header field
symbol and is in microseconds required to transmit the data
at the chosen data rate.
The packet consists of the preamble, header and MAC
protocol data unit (MPDU). The data is transmitted exactly as
received from the control processor. Some dummy bits will be
appended to the end of the packet to insure an orderly
shutdown of the transmitter. This prevents spectrum splatter.
At the end of a packet, the external controller is expected to
de-assert the TX_PE line to shut the transmitter down.
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consist of a 7-bit shift register with feedback from specified
taps of the register, as programmed through configuration
register CR 7. Both transmitter and receiver use the same
scrambling algorithm. The scrambler can be disabled by
setting the taps to 0.
NOTE: The IEEE 802.11 compliant scrambler in the HFA3860A has
the property that it can lock up (stop scrambling) on random data fol-
lowed by repetitive bit patterns. The probability of this happening is
1/128. The patterns that have been identified are all zeros, all ones,
repeated 10s, repeated 1100s, and repeated 111000s. Any break in
the repetitive pattern will restart the scrambler. If an all zeros pattern
following random data causes the scrambler to lock up and this state
lasts for more than 200 microseconds in the 5.5 and 11MBps data
modes, the demodulator may lose carrier tracking and corrupt the
packet. This is caused by a buildup of a DC bias in the AC coupling
between the HFA3724 and the HFA3860A.
PREAMBLE (SYNC)
128 BITS
SFD
16 BITS
SIGNAL FIELD
8 BITS
SERVICE FIELD
8 BITS
LENGTH FIELD
16 BITS
CRC16
16 BITS
HEADER
PREAMBLE
FIGURE 9. 802.11 PREAMBLE/HEADER
HFA3860A
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3860AIV | 3.3V 288-mc CPLD |
| HFA3861AIN96 | Circular Connector; No. of Contacts:21; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No |
| HFA3861AIN | 288 MACROCELL 3.3 VOLT ISP CPLD |
| HFA3863IN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3863IN96 | Direct Sequence Spread Spectrum Baseband Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860AEVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860AIV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
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