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参数资料
| 型号： | HFA3860A |
| 厂商： | Intersil Corporation |
| 英文描述： | Direct Sequence Spread Spectrum Baseband |
| 中文描述： | 直接序列扩频基带 |
| 文件页数： | 36/39页 |
| 文件大小： | 251K |
| 代理商： | HFA3860A |
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2-166
RX_PE Inactive Width
t
RLP
t
RCP
t
RCD
t
RDD
t
RD1
t
RD1
t
RDS
t
REH
t
REH
t
REH
t
REH
t
RD2
t
RD3
70
-
ns (Notes 9, 14)
RX_CLK Period (1MBps Mode)
77
-
ns
RX_CLK Width Hi or Low (11MBps Mode)
31
-
ns
RX_CLK to RXD
25
60
ns
MD_RDY to 1st RX_CLK
940
-
ns (Notes 9, 17)
RXD to 1st RX_CLK
940
-
ns
Setup RXD to RX_CLK
31
-
ns
RX_CLK to RX_PE Inactive (1MBps)
0
925
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (2MBps)
0
380
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (5.5MBps)
0
140
ns (Notes 9, 15)
RX_CLK to RX_PE Inactive (11MBps)
0
50
ns (Notes 9, 15)
RX_PE inactive to MD_RDY Inactive
5
30
ns (Note 16)
Last Chip of SFD in to MD_RDY Active
2.77
2.86
μ
s (Notes 9, 17)
RX Delay
2.77
2.86
μ
s (Notes 9, 18)
RESET Width Active
t
RPW
t
CCA
t
CCA
50
-
ns (Notes 9, 19)
RX_PE to CCA Valid
-
16
μ
s (Notes 9, 20)
RX_PE to RSSI Valid
-
16
μ
s (Notes 9, 20)
ANTSEL Lead Time
820
-
ns (Notes 9, 21)
SCLK Clock Period
t
SCP
t
SCW
t
SCS
t
SCH
t
SCD
t
SCED
t
D2
90
-
ns
SCLK Width Hi or Low
20
-
ns
Setup to SCLK + Edge (SD, SDI, R/W, CS)
30
-
ns
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
0
-
ns
SD Out Delay from SCLK + Edge
-
30
ns
SD Out Enable/Disable from R/W
-
15
ns (Note 9)
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
-
40
ns
NOTES:
8. AC tests performed with C
L
= 40pF, I
OL
= 2mA, and I
OH
= -1mA. Input reference level all inputs 1.5V. Test V
IH
= V
CC
,
V
IL
= 0V; V
OH
= V
OL
= V
CC
/2.
9. Not tested, but characterized at initial design and at major process/design changes, or guaranteed by design.
10. Measured from V
IL
to V
IH
.
11. Iout/Qout are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
12. TX_PE must be inactive before going active to generate a new packet.
13. Iout/Qout are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
14. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
15. RX_PE active to inactive delay to prevent next RX_CLK.
16. Assumes RX_PE inactive after last RX_CLK.
17. MD_RDY programmed to go active after SFD detect (measured from I
IN
, Q
IN
).
18. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at I
IN
, Q
IN
to MD_RDY active.
19. Minimum time to insure Reset. RESET must be followed by an RX_PE pulse to insure proper operation. This pulse should not be used for first receive
or acquisition.
20. CCA and RSSI are measured once during the first 16 us interval following RX_PE going active. RX_PE must be pulsed to initiate a new mea-
surement. RSSI may be read via serial port or from Test Bus.
21. ANTSEL is switched in diversity mode before acquisition cycle to compensate for delays in IF circuits. The correlators will be 100X(820ns -
TdRFns)/990 ns% full of new data at the beginning of bit sync accumulation. TdRFns is the settling time of the RF circuits after ANTSEL switches.
22. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
AC Electrical Specifications
V
CC
= 3.0V to 3.3V
±
10%, T
A
= -40
o
C to 85
o
C (Note 8)
(Continued)
PARAMETER
SYMBOL
MCLK = 44MHz
UNITS
MIN
MAX
HFA3860A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860AEVAL1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860AIV | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860AIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860AIV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Direct Sequence Spread Spectrum Baseband |
| HFA3860B | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:nullDirect Sequence Spread Spectrum Baseband Processor |
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