参数资料
型号: HFA3860A
厂商: Intersil Corporation
英文描述: Direct Sequence Spread Spectrum Baseband
中文描述: 直接序列扩频基带
文件页数: 28/39页
文件大小: 251K
代理商: HFA3860A
2-158
Bit 4
0 = Normal
1 = Delayed bit sync accumulation
Bit 3
0 = Normal
1 = Use multipath antenna selection (SQ3)
Bit 2
RX Diversity
0 = Off
1 = On
Single antenna, can use A or B (see bits 1:0).
Antenna switches during acquisition every 16 us. Starts cycle on antenna defined by bits 1:0.
Bits 1:0
CCA Antenna mode. Defines the antenna to be used at the start of acquisition for CCA checking and for subsequent trans-
mission. TX antenna is always the same as used to check CCA. Controls antenna selection via the ANT_SEL pin.
00 = Use last Receive antenna for CCA checking and TX. Acquisition starts on the antenna which had a valid header on last
reception.
01 = Illegal State - Unknown Behavior
10 = Use antenna B for CCA and TX (single antenna). AntSel = 0
11 = Use antenna A for CCA and TX (single antenna). AntSel = 1
CONFIGURATION REGISTER 5 ADDRESS (14h) CCA ANTENNA CONTROL (Continued)
CONFIGURATION REGISTER 6 ADDRESS (18h) PREAMBLE LENGTH
Bits 0 - 7
This register contains the count for the Preamble length counter. Setup while TX_PE is low. For IEEE 802.11 use 80h. For
other than IEEE 802.11 applications, in general increasing the preamble length will improve low signal to noise acquisition
performanceatthecostofgreaterlinkoverhead.Fordualreceiveantennaoperation,theminimumsuggestedvalueis128d=80h.
For single receive antenna operation, the minimum suggested value is 80d = 50h. These suggested values include a 2 symbol TX
power amplifier ramp up. If you program 128 you get 130.
CONFIGURATION REGISTER 7 ADDRESS (1Ch) SCRAMBLER TAPS
Bit 7
0 = Normal, RX_PE Enables/Disables the internal receive clock. I = Internal receive clock is always enabled.
Bits 6:0
This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scrambler is
a 7-bit shift register, with 7 configurable taps. A logic 1 is the respective bit position enables that particular tap. The example
below illustrates the register configuration for the polynomial F(x) = 1 + X
-4
+X
-7
. Each clock is a shift left.
LSB
Bits (6:0)
6 5 4 3 2 1 0
X
-7
X
-6
X
-5
X
4
X
-3
X
-2
X
-1
Term
Scrambler Taps
F(x) = 1 + X
-4
+X
-7
1 0 0 1 0 0 0
CONFIGURATION REGISTER 8 ADDRESS (20h) SQ1 ACQ THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurements made during acquisition at each antenna dwell. This threshold comparison is added with the SQ2 threshold
in registers 10 and 11 for acquisition. A lower value on this threshold will increase the probability of detection and the
probability of false alarm.
CONFIGURATION REGISTER 9 ADDRESS (24h) SQ1 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition at each antenna dwell.
CONFIGURATION REGISTER 10 ADDRESS (28h) SQ2 ACQ THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8-15) of the carrier phase variance threshold used for acquisition. This
register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made
during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used with the bit
sync threshold in registers 8 and 9 to declare acquisition. A higher value in this threshold will increase the probability of
acquisition and false alarm.
HFA3860A
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