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参数资料
| 型号： | HFA3860BIV |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件页数： | 12/40页 |
| 文件大小： | 272K |
| 代理商： | HFA3860BIV |
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4-12
Power Down Modes
The power consumption modes of the HFA3860B are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 33), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 2), which disables the
transmitter when inactive.
Reset (RESET, pin 28), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a maximum
of 10
μ
s before the device is back at its operational mode for
transmitters. Add 5ms more to be operational for receive
mode. It also requires that RX_PE be activated briefly to
clock in the change of state.
The contents of the Configuration Registers are not effected
by any of the power down modes. The external processor
does have access and can modify any of the CRs during the
power down modes. No reconfiguration is required when
returning to operational modes.
Table 6 describes the power down modes available for the
HFA3860B (V
CC
= 3.3V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
Transmitter Description
The HFA3860B transmitter is designed as a Direct
Sequence Spread Spectrum Phase Shift Keying (DSSS
PSK) modulator. It can handle data rates of up to 11MBPS
(refer to AC and DC specifications). Two different
modulations are available for the 5.5Mbps and 11Mbps
modes. This is to accommodate backwards compatibility
with the HFA3860A and to provide an IEEE 802.11
standards compliant mode. The various modes of the
modulator are Differential Binary Phase Shift Keying
(DBPSK) for 1Mbps, Differential Quaternary Phase Shift
Keying (DQPSK) for 2Mbps, Binary M-ary Bi-Orthogonal
Keying (BMBOK) or Complementary Code Keying (CCK) for
5.5Mbps, and Quaternary M-ary Bi-Orthogonal Keying
(QMBOK) or CCK for 11Mbps. These implement data rates
as shown in Table 7. The major functional blocks of the
transmitter include a network processor interface, DPSK
modulator, high rate modulator, a data scrambler and a
spreader, as shown on Figure 11. A description of (M-ARY)
Bi-Orthogonal Keying can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing. CCK is essentially a
quadraphase form of that modulation.
The preamble and header are always transmitted as DBPSK
waveforms while the data packets can be configured to be
either DBPSK, DQPSK, BMBOK, QMBOK, or CCK. The
preamble is used by the receiver to achieve initial PN
synchronization while the header includes the necessary
data fields of the communications protocol to establish the
physical layer link. The transmitter generates the
synchronization preamble and header and knows when to
make the DBPSK to DQPSK or B/QMBOK or CCK
switchover, as required.
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and mixes it with the BPSK
PN spreading. The baseband digital signals are then output
to the external IF modulator.
For the MBOK modes, the transmitter inputs the data and
forms it into nibbles (4 bits). At 5.5Mbps, it selects one of 8
spread sequences from a table of sequences with 3 of those
bits and then picks the true or inverted version of that
sequence with the remaining bit. Thus, there are 16 possible
spread sequences to send, but only one is sent. This
sequence is then modulated on both the I and Q outputs.
The phase of the last bit of the header is used as an
absolute phase reference for the data portion of the packet.
At 11Mbps, two nibbles are used, and each one is used as
above independently. One of the resulting sequences is
modulated on the I Channel and the other on the Q Channel
output. With 16 possible sequences on I and another 16
independently on Q, the total possible number of
combinations is 256. Of these only one is sent.
For the CCK modes, the transmitter inputs the data and
forms it into nibbles (4 bits) or bytes (8 bits). At 5.5MBPS, it
selects one of 4 complex spread sequences as a symbol
from a table of sequences with 2 of those bits and then
QPSK modulates that symbol with the remaining 2 bits.
Thus, there are 16 possible spread sequences to send, but
only one is sent. This sequence is then modulated on the I
and Q outputs jointly. The phase of the last bit of the header
is used as a phase reference for the data portion of the
packet. At 11Mbps, one byte is used as above with 6 bits
used to select one of 64 spread sequences for a symbol and
the other 2 used to QPSK modulate that symbol. Thus, the
total possible number of combinations is 256. Of these only
one is sent.
HFA3860B
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3860BIV96 | nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860IV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
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