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参数资料
| 型号： | HFA3860BIV |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件页数： | 18/40页 |
| 文件大小： | 272K |
| 代理商： | HFA3860BIV |
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4-18
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, BMBOK, QMBOK, or CCK symbols. The
demodulator includes a frequency tracking loop that tracks
and removes the carrier frequency offset. In addition it tracks
the symbol timing, and differentially decodes (where
appropriate) and descrambles the data. The data is output
through the RX Port to the external processor.
The PRISM baseband processor, HFA3860B uses differential
demodulation for the initial acquisition portion of the message
processing and then switches to coherent demodulation for
the rest of the acquisition and data demodulation. The
HFA3860B is designed to achieve rapid settling of the carrier
tracking loop during acquisition. Rapid phase fluctuations are
handled with a relatively wide loop bandwidth. Coherent
processing improves the BER performance margin as
opposed to differentially coherent processing and is
necessary for processing the MBOK data rates.
The baseband processor uses time invariant correlation to
strip the PN spreading and phase processing to demodulate
the resulting signals in the header and DBPSK/DQPSK
demodulation modes. These operations are illustrated in
Figure 15 which is an overall block diagram of the receiver
processor.
In processing the DBPSK header, input samples from the I and
Q A/D converters are correlated to remove the spreading
sequence. The peak position of the correlation pulse is used to
determine the symbol timing. The sample stream is decimated
to the symbol rate and the phase is corrected for frequency
offset prior to PSK demodulation. Phase errors from the
demodulator are fed to the NCO through a lead/lag filter to
maintain phase lock. The variance of the phase error is used to
determine signal quality for acquisition and lock detection. The
demodulated data is differentially decoded and descrambled
before being sent to the header detection section.
In the 1MBPS DBPSK mode, data demodulation is
performed the same as in header processing. In the
2MBPS DQPSK mode, the demodulator demodulates two
bits per symbol and differentially decodes these bit pairs.
The bits are then serialized and descrambled prior to being
sent to the output.
In the MBOK and CCK modes, the receiver uses a complex
multiplier to remove carrier frequency offsets and a bank of
correlators to detect the modulation. A biggest picker finds the
largest correlation in the I and Q Channels and determines
the sign of those correlations. For this to happen, the
demodulator must know absolute phase which is determined
by referencing the data to the last bit of the header. Each
symbol demodulated determines 1 or 2 nibbles of data.
This is then serialized and descrambled before passing on to
the output.
Chip tracking in the MBOK and CCK modes is chip decision
directed. Carrier tracking is via a lead/lag filter using a digital
Costas phase detector.
Acquisition Description
The PRISM baseband processor uses either a dual antenna
mode of operation for compensation against multipath
interference losses or a single antenna mode of operation
with faster acquisition times.
Two Antenna Acquisition
(Recommended for Indoor Use)
During the 2 antenna (diversity) mode the two antennas are
scanned in order to find the one with the best representation
of the signal. This scanning is stopped once a suitable signal
is found and the best antenna is selected.
A projected worst case time line for the acquisition of a
signal in the two antenna case is shown in Figure 12. The
synchronization part of the preamble is 128 symbols long
followed by a 16-bit SFD. The receiver must scan the two
antennas to determine if a signal is present on either one
and, if so, which has the better signal. The timeline is
broken into 16 symbol blocks (dwells) for the scanning
process. This length of time is necessary to allow enough
integration of the signal to make a good acquisition
decision. This worst case time line example assumes that
the signal is present on antenna A1 only (A2 is blocked). It
further assumes that the signal arrives part way into the
first A1 dwell such as to just barely miss detection. The
signal and the scanning process are asynchronous and the
signal could start anywhere. In this timeline, it is assumed
that all 16 symbols are present, but they were missed due
to power amplifier ramp up. Since A2 has insufficient
signal, the first A2 dwell after the start of the preamble also
fails detection. The second A1 dwell after signal start is
successful and a symbol timing measurement is achieved.
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. When the bit sync level, SQ1, and Phase
variance SQ2 are above their user programmable
thresholds, the signal is declared present for that antenna.
More details on the Signal Quality estimates and their
programmability are given in the Acquisition Signal Quality
Parameters section of this document.
At the end of each dwell, a decision is made based on the
relative values of the signal qualities of the signals on the two
antennas. In the example, antenna A1 is the one selected, so
the recorded symbol timing and carrier frequency for A1 are
used thereafter for the symbol timing and the PLL of the NCO
to begin carrier de-rotation and demodulation.
Prior to initial acquisition the NCO was inactive and DPSK
demodulation processing was used. Carrier phase
measurement are done on a symbol by symbol basis
afterward and coherent DPSK demodulation is in effect.
HFA3860B
相关PDF资料 |
PDF描述 |
|---|---|
| HFA3860BIV96 | nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860IV96 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
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