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参数资料
| 型号： | HM62V8512BLFP-8 |
| 元件分类： | SRAM |
| 英文描述： | STANDARD SRAM, PDSO32 |
| 封装： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件页数： | 16/17页 |
| 文件大小： | 77K |
| 代理商： | HM62V8512BLFP-8 |
HM62V8512B Series
8
Write Cycle
HM62V8512B
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
70
—
85
—
ns
Chip selection to end of write
t
CW
60
—
75
—
ns
4
Address setup time
t
AS
0—
ns
5
Address valid to end of write
t
AW
60
—
75
—
ns
Write pulse width
t
WP
50
—
55
—
ns
3, 12
Write recovery time
t
WR
0—
ns
6
WE to output in high-Z
t
WHZ
0
30
0
35
ns
1, 2, 7
Data to write time overlap
t
DW
30
—
35
—
ns
Data hold from write time
t
DH
0—
ns
Output active from output in high-Z
t
OW
5—
ns
2
Output disable to output in high-Z
t
OHZ
0
30
0
35
ns
1, 2, 7
Notes: 1. t
HZ, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
WP) of a low CS and a low WE.
A write begins at the later
transition of
CS going low or WE going low. A write ends at the earlier transition of CS going high
or
WE going high. t
WP is measured from the beginning of write to the end of write.
4. t
CW is measured from CS going low to the end of write.
5. t
AS is measured from the address valid to the beginning of write.
6. t
WR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the
CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If
CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with
OE low fixed, t
WP must satisfy the following equation to avoid a problem of
data bus contention. t
WP ≥ tDW min + tWHZ max
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