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参数资料
| 型号： | HM62V8512BLFP-8 |
| 元件分类： | SRAM |
| 英文描述： | STANDARD SRAM, PDSO32 |
| 封装： | 0.525 INCH, PLASTIC, SOP-32 |
| 文件页数： | 4/17页 |
| 文件大小： | 77K |
| 代理商： | HM62V8512BLFP-8 |
HM62V8512B Series
12
Low V
CC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*
4
V
CC for data retention
V
DR
2—
—
V
CS
≥ V
CC – 0.2 V, Vin ≥ 0 V
Data retention current
I
CCDR
—
0.8*
5
20*
1
AV
CC = 3.0 V, Vin ≥ 0 V
CS
≥ V
CC – 0.2 V
—
0.8*
5
10*
2
A
—
0.8*
5
2*
3
A
Chip deselect to data retention time
t
CDR
0
—
ns
See retention waveform
Operation recovery time
t
R
t
RC*
6
——
ns
Notes: 1. For L-version and 10
A (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 3
A (max.) at Ta = –20 to +40°C.
3. For L-UL-version and 2
A (max.) at Ta = –20 to +40°C.
4.
CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address,
WE, OE, I/O) can be in the high impedance state.
5. Typical values are at V
CC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
6. t
RC = read cycle time.
Low V
CC Data Retention Timing Waveform (CS Controlled)
CC
V
2.7 V
2.0 V
0 V
CS
tCDR
tR
CS
V
– 0.2 V
CC
≥
DR
V
Data retention mode
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