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参数资料
| 型号： | HM66WP18513BP-65 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封装： | BGA-119 |
| 文件页数： | 1/31页 |
| 文件大小： | 268K |
| 代理商： | HM66WP18513BP-65 |
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Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HM66WP18513/HM66WP36257
9M Flow Through Zero Bus Latency (ZBL) SRAM
(HM66WP18513) 512-Kword
× 18-bit
(HM66WP36257) 256-Kword
× 36-bit
ADE-203-1285C (Z)
Preliminary
Rev. 0.3
Mar. 29, 2002
Description
The HM66WP18513 is a synchronous fast static RAM organized as 512-Kword
× 18-bit. The
HM66WP36257 is a synchronous fast static RAM organized as 256-Kword
× 36-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 100-
pin LQFP and 119-pin BGA.
Note : All power supply(V
DD,VDDQ) and ground(VSS) pins must be connected for proper operation of the
device.
ZBL : Zero Bus Latency and compatible ZBT
TM SRAM. ZBTTM is trademark of Integrated Device
Technology, Inc.,
Features
3.3 V or 2.5V power supply, 3.3 V or 2.5 V I/O supply voltage
Clock frequency: 133/117/100 MHz
Fast clock access time: 6.5/7.5/8.5 ns (max)
Low operating current: 200/180/160 mA (max)
Address data pipeline capability
Internal input registers (Address, Data, Control)
Internal self-timed write cycle
ADV/LD burst control pins
Asynchronous output enable controlled three-state outputs
Individual byte write control
Power down state via ZZ
Common data inputs and data outputs
High board density 100-pin LQFP package and 119-pin BGA package
Burst control selected pin LBO (Interleave or linear burst oder)
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