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参数资料
| 型号： | HM66WP18513BP-65 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封装： | BGA-119 |
| 文件页数： | 30/31页 |
| 文件大小： | 268K |
| 代理商： | HM66WP18513BP-65 |
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HM66WP18513, HM66WP36257
Rev.0.3, Mar. 2002, page 8 of 31
Detailed Pin Description
(cont)
Pin number(s)
LQFP
BGA
Symbol
Type
Description
38, 39, 42, 43, 84
1B, 1C, 1R, 1T, 3J, 4A, 4D,
4L,5J,5R,6T,6U,7B,7C,7R
NC
(
× 36-bit)
—
No Connect: These signals are
internally not connected.
1, 2, 3, 6, 7, 25, 28, 29,
30, 38, 39, 42, 43, 51,
52, 53, 56, 57, 75, 78,
79, 84, 95, 96
1B, 1C, 1E, 1G, 1K, 1P, 1R,
1T,2D,2F,2H,2L,2N,4A,4L,
4T,5J,5R,6E,6G,6K,6M,6P,
6U,7B,7C,7D,7H,7L,7N,7R
NC
(
× 18-bit)
—
No Connect: These signals are
internally not connected.
51, 52, 53, 56, 57, 58,
59, 62, 63, 68, 69, 72,
73, 74, 75, 78, 79, 80,
1, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24,
25, 28, 29, 30
6K, 6L, 6M, 6N, 6P, 7K,
7L, 7N, 7P, 6D, 6E, 6F,
6G, 6H, 7D, 7E, 7G, 7H,
1D, 1E, 1G, 1H, 2D, 2E
2F, 2G, 2H, 1K, 1L, 1N
1P,2K , 2L, 2M, 2N, 2P
DQmn
m = a, b,
c, d
n = 0 – 8
(
× 36-bit)
Input/
Output
SRAM data I/O: Byte a is DQa0
to DQa8; Byte b is DQb0 to
DQb8; Byte c is DQc0 to DQc8;
Byte d is DQd0 to DQd8. Input
data must meet setup and hold
times around the rising edge of
CLK.
58, 59, 62, 63, 68, 69,
72, 73, 74, 8, 9, 12, 13,
18, 19, 22, 23, 24
6D, 6F, 6H, 6L, 6N, 7E,
7G, 7K, 7P, 1D, 1H, 1L,
1N, 1E, 1G, 1K, 1M, 1P
DQmn
m = a, b
n = 0 – 8
(
× 18-bit)
Input/
Output
SRAM data I/O: Byte a is DQa0
to DQa8; Byte b is DQb0 to
DQb8. Input data must meet
setup and hold times around the
rising edge of CLK.
15, 16, 41, 65, 91
2J, 4C, 4J, 4R, 6J,
V
DD
Supply
Power supply: 3.3 V (+5%/–5%)
or 2.5 V (+5%/–5%)
4, 11, 20, 27, 54
61, 70, 77
1A, 1F, 1J, 1M, 1U,
7A, 7F, 7J, 7M, 7U
V
DDQ
Supply
I/O power supply:
3.3 V (+5%/–5%)
or 2.5 V (+5%/–5%)
14, 17, 40, 66, 67, 90,
5, 10, 21, 26, 55, 60,
71, 76
3D,3E,3F,3H,3K,3M,3N,3P,
5D,5E,5F,5H,5K,5M,5N,5P
V
SS
Supply
Ground: GND
3L, 5G
V
SS
(
× 18-bit)
Supply
Ground: GND
64
7T
ZZ
Input
Asynchronous power-down
(Snooze): This active HIGH
input enables SRAM to enter a
power-down (Snooze) state with
data retention. During Snooze
state, data retention is
guaranteed. At this time,
internal state of the SRAM is not
preserved. After Snooze state,
SRAM must be initiated with
CEN or ADV/LD using a new
external address. This pin must
be connected to V
SS in systems
that do not use ZZ feature.
31
3R
LBO
Input
Burst order (Interleave burst or
linear burst) select pin (DC)
This pin must connect V
DD or VDDQ
or V
SS.
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