- 您现在的位置：买卖IC网 > PDF目录223983 > HM66WP18513BP-65 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 PDF资料下载
参数资料
| 型号： | HM66WP18513BP-65 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 6.5 ns, PBGA119 |
| 封装： | BGA-119 |
| 文件页数： | 29/31页 |
| 文件大小： | 268K |
| 代理商： | HM66WP18513BP-65 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页
HM66WP18513, HM66WP36257
Rev.0.3, Mar. 2002, page 7 of 31
Detailed Pin Description
Pin number(s)
LQFP
BGA
Symbol
Type Description
35, 34, 33, 32,
44, 45, 46, 47,
48, 49, 50, 81,
82, 83, 99, 100
37, 36
2A, 2C, 2R, 3A,
3B, 3C, 3T, 4G,
5A, 5B, 5C, 5T,
6A, 6C, 6R
4P, 4N
A
(
× 36-bit
× 18-bit
common)
A0,A1
Input Synchronous address inputs: These inputs are
registered and must meet setup and hold times
around the rising edge of CLK
. Burst address inputs
80
2T, 6T
4T
A (
× 18-bit)
A (
× 36-bit)
93, 94,
95, 96
5L, 5G,
3G, 3L
BWa, BWb
BWc, BWd
(
× 36-bit)
Input Synchronous byte write enables: These active LOW
inputs allow individual bytes to be written and must
meet the setup and hold times around the rising edge
of CLK. A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle.
BWa controls
DQa0 to DQa8.
BWb controls DQb0 to DQb8. BWc
controls DQc0 to DQc8.
BWd controls DQd0 to
DQd8. Data I/O are tri-stated if any of these four
inputs are LOW.
93, 94
5L, 3G
BWa, BWb
(
× 18-bit)
87
4M
CEN
Input Synchronous clock enable: This active LOW internal
clock signal is active.
88
4H
WE
Input Synchronous write enable: This active LOW input
permits write operations and must meet the setup and
hold times around the rising edge of CLK.
89
4K
CLK
Input Clock: This signal latches the address, data, chip
enables, byte write enables and burst control inputs
on its rising edge. All synchronous inputs must meet
setup and hold times around the clock's rising edge.
98
4E
CE1
Input Synchronous chip enables: This active LOW input is
used to enable the device. This input is sampled only
when a external address is loaded. This input can be
used for memory depth expansion.
92
6B
CE3
Input
97
2B
CE2
Input Synchronous chip enable: This active HIGH input is
used to enable the device. This input sampled only
when a new external address is load. This input can
be used for memory depth expansion.
86
4F
OE
Input Output enable: This active LOW asynchronous input
enables the data I/O output drivers.
85
4B
ADV/
LD
Input Synchronous address advance or load control: This
active HIGH input is used to advance the internal
burst counter, controlling burst access after the
external address is loaded. A LOW input is caused a
new external address to be latched.
相关PDF资料 |
PDF描述 |
|---|---|
| HM6AEB36105BP40 | 1M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| HM76-408R2J | DATA LINE FILTER |
| HM76-40820J | DATA LINE FILTER |
| HM76-406R8J | DATA LINE FILTER |
| HM76-40681J | DATA LINE FILTER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HM67 | 制造商:BITECH 制造商全称:Bi technologies 功能描述:Surface Mount Common Mode Chokes |
| HM6707AJP-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x1 SRAM |
| HM6707AJP-15T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x1 SRAM |
| HM6707AJP-20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x1 SRAM |
| HM6707AJP-25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x1 SRAM |
发布紧急采购，3分钟左右您将得到回复。