参数资料
| 型号： | HMP8156ACNZ |
| 厂商： | Intersil |
| 文件页数： | 15/34页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO ENCODER NTSC/PAL 64MQFP |
| 标准包装： | 84 |
| 类型： | NTSC/PAL 编码器 |
| 应用： | 多媒体，视频编辑 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-MQFP（14x14） |
| 包装： | 托盘 |
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22
FN4343.5
August 20, 2009
TABLE 22. CLOSED CAPTION_284B DATA REGISTER
SUB ADDRESS = 13H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Line 284 Caption
Data
(Second Byte)
This register is cascaded with the closed caption_284A data register and they are read out
serially as 16 bits during line 281, 284, or 335 if line 284 captioning is enabled. Bit D0 of the
284A data register is shifted out first.
80H
TABLE 23. START H_BLANK LOW REGISTER
SUB ADDRESS = 20H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
(Horizontal)
This 8-bit register is cascaded with Start H_Blank High Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1X clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
4AH
TABLE 24. START H_BLANK HIGH REGISTER
SUB ADDRESS = 21H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-2
Reserved
000000B
1-0
Assert BLANK
Output Signal
(Horizontal)
This 2-bit register is cascaded with Start H_Blank Low Register to form a 10-bit
start_horizontal_blank register. It specifies the horizontal count (in 1x clock cycles) at which to
start ignoring pixel data each scan line. The leading edge of HSYNC is count 020H. This
register is ignored unless BLANK is configured as an output.
11B
TABLE 25. END H_BLANK REGISTER
SUB ADDRESS = 22H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
(Horizontal)
This 8-bit register specifies the horizontal count (in 1X clock cycles) at which to start inputting
pixel data each scan line. The leading edge of HSYNC is count 000H. This register is ignored
unless BLANK is configured as an output.
7AH
TABLE 26. START V_BLANK LOW REGISTER
SUB ADDRESS = 23H
BIT
NUMBER
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Assert BLANK
Output Signal
(Vertical)
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to start
ignoring pixel input data (and what line number to start blanking the output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start ignoring pixel
input data each noninterlaced input frame. The output video will be blanked starting on line
number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000H (note that this does not
follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is
configured as an output.
03H
HMP8154, HMP8156A
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相关代理商/技术参数 |
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|---|---|
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8170 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8170_03 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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