参数资料
| 型号： | HMP8156ACNZ |
| 厂商： | Intersil |
| 文件页数： | 31/34页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO ENCODER NTSC/PAL 64MQFP |
| 标准包装： | 84 |
| 类型： | NTSC/PAL 编码器 |
| 应用： | 多媒体，视频编辑 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-MQFP（14x14） |
| 包装： | 托盘 |
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6
FN4343.5
August 20, 2009
Normal 8-Bit YCbCr Format
When 8-bit YCbCr format is selected and 2X upscaling or
flicker filtering is not enabled, the data is latched on each
rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y
Cr Y’ . . . ], with the first active data each scan line being Cb
data. Overlay data is latched when the Y input data is latched.
The pixel and overlay input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
8-Bit YCbCr Format with 2X Upscaling
When 8-bit YCbCr format is selected and 2X upscaling is
enabled, the data is latched on the rising edge of CLK2 while
CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr
Y’. . . ], with the first active data each scan line being Cb
data. Overlay data is latched on the rising edge of CLK2 that
latches Y pixel input data. The pixel and overlay input timing
is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In this mode of operation, CLK is
one-half the CLK2 frequency.
TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
INPUT FORMAT
MODE
(NO
T
E
1
)
INPUT PORT SAMPLING
VIDEO TIMING CONTROL (NOTE 2)
CLK FREQUENCY
PIXEL DATA
OVERLAY DATA
INPUT SAMPLE
OUTPUT ON
INPUT
OUTPUT
8-Bit YCbCr
Norm
Every rising edge
of CLK2
Same edge that
latches Y
Every rising edge
of CLK2
Any rising edge of
CLK2
Ignored
One-half
CLK2
2X
Rising edge of
CLK2 when CLK is
low.
Same edge that
latches Y data
Rising edge of
CLK2 when CLK is
low.
Rising edge of
CLK2 when CLK is
high.
One-half CLK2
FF
Not Available
16-Bit YCbCr,
16-Bit RGB,
or
24-Bit RGB
Norm
Rising edge of CLK2 when CLK is low
Rising edge of
CLK2 when CLK is
high.
One-half CLK2
2X
2nd rising edge of CLK2 when CLK is low
Either rising CLK2
edge when CLK is
high
One-fourth CLK2
FF
Every rising edge
of CLK2
Same edge that
latches Y
Every rising edge
of CLK2
Any rising edge of
CLK2
Ignored
One-half
CLK2
BT.656
Norm
Every rising edge
of CLK2
Same edge that
latches Y
Not Allowed
Any rising edge of
CLK2
Ignored
One-half
CLK2
2X
Not Available
FF
Not Available
NOTES:
1. Encoder operating modes:
Norm = Full size input, Flicker filter disabled.
2X = SIF size input, Flicker filter disabled.
FF = Full size input, Flicker filter enabled.
(2X upscaling and flicker filtering are mutually exclusive.)
2. Video timing control signals include HSYNC, VSYNC, BLANK and FIELD. The sync and blanking I/O directions are independent; FIELD is always
an output.
HMP8154, HMP8156A
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相关代理商/技术参数 |
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|---|---|
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8170 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8170_03 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
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