参数资料
型号: HMP8156ACNZ
厂商: Intersil
文件页数: 17/34页
文件大小: 0K
描述: IC VIDEO ENCODER NTSC/PAL 64MQFP
标准包装: 84
类型: NTSC/PAL 编码器
应用: 多媒体,视频编辑
电压 - 电源,模拟: 4.75 V ~ 5.25 V
电压 - 电源,数字: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 64-BQFP
供应商设备封装: 64-MQFP(14x14)
包装: 托盘
24
FN4343.5
August 20, 2009
Pinout
HMP8154/HMP8156A
(PQFP)
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
COMP
1
COMP
2
FS_ADJUST
VREF
GND
P0
V
AA
GND
P1
P2
P3
P4
P5
P6
P7
VAA
Y/G
C/B
GND
VAA
GND
NTSC/PAL1
GN
D
GND
NTSC/PAL2
GND
VAA
GND
VAA
SC
L
SDA
SA
RESV
P2
3
P2
2
VA
A
RESE
T
GN
D
P2
1
OL
1/
P17
M0/
P
19
OL
2/
P18
M1/
P
20
OL
0/
P16
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P8
P9
P10
P11
P12
P13
GND
CLK2
VAA
CLK
P14
P15
VSYNC
HSYNC
FIELD
BLANK
Pin Descriptions
PIN
NAME
PIN
NUMBER
INPUT/
OUTPUT
DESCRIPTION
P0-P15
58, 55-43,
38, 37
I
Pixel input pins. See Table 1. Any pixel inputs not used should be connected to GND.
P16-P23
32-27, 23,
22
I
Overlay or pixel inputs. See Table 1. Any overlay or pixel inputs not used should be
connected to GND.
RESV
21
I
This pin is reserved and should be connected to VCC or GND.
FIELD
34
O
FIELD output. The field output indicates that the encoder is outputting the odd or even video
field. The polarity of FIELD is programmable.
HSYNC
35
I/O
Horizontal sync input/output. As an input, this pin must be asserted during the horizontal
sync intervals. If it occurs early, the line time will be shortened. If it occurs late, the line time
will be lengthened by holding the outputs at the front porch level. As an output, it is
asserted during the horizontal sync intervals. The polarity of HSYNC is programmable. If
not driven, the circuit for this pin should include a 4-12k
Ω pull up resistor connected to
VAA.
VSYNC
36
I/O
Vertical sync input/output. As an input, this pin must be asserted during the vertical sync
intervals. If it occurs early, the field time will be shortened. If it occurs late, the field time
will be lengthened by holding the outputs at the blanking level. As an output, it is asserted
during the vertical sync intervals. The polarity of VSYNC is programmable. If not driven,
the circuit for this pin should include a 4-12k
Ω pull up resistor connected to VAA.
BLANK
33
I/O
Composite blanking input/output. As an input, this pin must be asserted during the
horizontal and vertical blanking intervals. As an output, it is asserted during the horizontal
and vertical blanking intervals. The polarity of BLANK is programmable. If not driven, the
circuit for this pin should include a 4-12k
Ω pull up resistor connected to VAA.
HMP8154, HMP8156A
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