参数资料
| 型号： | HMP8156ACNZ |
| 厂商： | Intersil |
| 文件页数： | 3/34页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO ENCODER NTSC/PAL 64MQFP |
| 标准包装： | 84 |
| 类型： | NTSC/PAL 编码器 |
| 应用： | 多媒体，视频编辑 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 电压 - 电源，数字： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-BQFP |
| 供应商设备封装： | 64-MQFP（14x14） |
| 包装： | 托盘 |
第1页第2页当前第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
11
FN4343.5
August 20, 2009
8-Bit BT.656 Format
When BT.656 format is selected, data is latched on each
rising edge of CLK2. Overlay data is latched when the Y
input data is latched. However, the overlay data must arrive
three pixels after its corresponding Y data. The pixel and
overlay input timing is shown in Figure 12.
As inputs, the BLANK, HSYNC, and VSYNC pins are
ignored since all timing is derived from the EAV and SAV
sequences within the data stream. As outputs, BLANK,
HSYNC and VSYNC are output following the rising edge of
CLK2. If the CLK pin is configured as an input, it is ignored. If
configured as an output, it is one-half the CLK2 frequency.
Square pixel operation, overlay processing with internal
mixing, flicker filtering, and SIF mode 2X upsampling are not
supported for the BT.656 input format. Also, the HSYNC,
VSYNC, and BLANK signals must be configured as outputs.
Video Timing Control
Regardless of the input mode, the output video timing of the
HMP8154/HMP8156A is at 50 or 59.94 fields per second
(interlaced). For normal and 2X upscaling modes, the pixel
input timing is at 50 or 59.94 fields per second; with the
flicker filter enabled, the input timing rate is twice as fast.
The output video and pixel input timing is controlled by the
BLANK, HSYNC, VSYNC, FIELD, and CLK2 pins.
HSYNC, VSYNC, and Field Timing
The leading edge of HSYNC indicates the beginning of a
horizontal sync interval. If HSYNC is an output, it is asserted
for about 4.7
μs. If HSYNC is an input, it must be active for at
least two CLK2 periods. The width of the horizontal
composite sync tip is determined from the video standard
and does not depend on the width of HSYNC.
The leading edge of VSYNC indicates the beginning of a
vertical sync interval. If VSYNC is an output, it is asserted for
3 scan lines in (M, NSM) NTSC and (M, N) PAL modes or
2.5 scan lines in (B, D, G, H, I, CN) PAL modes. If VSYNC is
an input, it must be asserted for at least two CLK2 periods.
When HSYNC and VSYNC are configured as outputs, their
leading edges will occur simultaneously at the start of an odd
field. At the start of an even field, the leading edge of
VSYNC occurs in the middle of the line.
When HSYNC and VSYNC are configured as inputs, the
HMP8154/HMP8156A provides a programmable HSYNC
window for determining FIELD. The window is specified with
respect to the leading or trailing edge of VSYNC. The edge
is selected in the field control register. When HSYNC is
found inside the window, then the encoder sets FIELD to the
value specified in the field control register.
The HMP8154/HMP8156A provides programmable timing
for the VSYNC input. At the active edge of VSYNC, the
encoder resets its vertical half-line counter to the value
specified by the field control register. This allows the input
and output syncs to be offset, although the data must still be
aligned.
The FIELD signal is always an output and changes state
near each leading edge of VSYNC. The delay between the
syncs and FIELD depends on the encoder’s operating mode
as summarized in Table 6. In modes in which the encoder
uses CLK to gate its inputs and outputs, the FIELD signal
may be delayed 0-12 additional CLK2 periods.
Figure 13 illustrates the HSYNC, VSYNC, and FIELD
general timing for (M, NSM) NTSC and (M, N) PAL. Figure
14 illustrates the general timing for (B, D, G, H, I, CN) PAL. In
the figures, all the signals are shown active low (their reset
state), and FIELD is low during odd fields.
FIGURE 12. PIXEL AND OVERLAY INPUT TIMING - BT.656
Cb 2
Y 2
Cr 2
Y 3
Cb 4
Y 4
CLK2
P8-P15
PIXEL 0
PIXEL 1
OL0-OL2,
M1, M0
"FF"
"00"
BLANK
(OUTPUT)
"00"
"XY"
"10"
PIXEL N-2
PIXEL N-1
"10"
"80"
PIXEL N
TABLE 6. FIELD OUTPUT TIMING
OPERATING MODE
CLK2
DELAY
COMMENTS
SYNC I/O
DIRECTION
BLANK I/O
DIRECTION
Input
148
FIELD lags VSYNC
switching from odd to even.
FIELD lags the earlier of
VSYNC and HSYNC when
syncs are aligned when
switching from even to odd.
Input
Output
138
FIELD lags VSYNC.
Output
Don’t Care
32
FIELD leads VSYNC.
HMP8154, HMP8156A
相关PDF资料 |
PDF描述 |
|---|---|
| HSP45102SC-40Z | IC OSC NCO 40MHZ 28-SOIC |
| HSP45106JC-33Z | IC OSC NCO 33MHZ 84-PLCC |
| HSP45116AVC-52Z | IC OSC NCO 52MHZ 160-MQFP |
| ICL7109EPL+ | IC ADC 12BIT 3-ST 40-DIP |
| ICM7217AIPI | IC OSC UP/DWN CNTR 2MHZ 28-DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8170 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
| HMP8170_03 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:NTSC/PAL Video Encoder |
发布紧急采购，3分钟左右您将得到回复。