参数资料
型号: HSP43124SC-45Z
厂商: Intersil
文件页数: 1/18页
文件大小: 0K
描述: IC I/O FILTER SER 24BIT 28-SOIC
标准包装: 26
滤波器类型: 串行输入/输出
滤波器数: 6
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
1
FN3555.7
HSP43124
Serial I/O Filter
The Serial I/O Filter is a high performance filter engine that is
ideal for off loading the burden of filter processing from a DSP
microprocessor. It supports a variety of multistage filter
configurations based on a user programmable filter and fixed
coefficient halfband filters. These configurations include a
programmable FIR filter of up to 256 taps, a cascade of from
one to five halfband filters, or a cascade of halfband filters
followed by a programmable FIR. The half band filters each
decimate by a factor of two, and the FIR filter decimates from
one to eight. When all six filters are selected, a maximum
decimation of 256 is provided.
For digital tuning applications, a separate multiplier is provided
which allows the incoming data stream to be multiplied, or
mixed, by a user supplied mix factor. A two pin interface is
provided for serially loading the mix factor from an external
source or selecting the mix factor from an on-board ROM. The
on-board ROM contains samples of a sinusoid capable of
spectrally shifting the input data by one quarter of the sample
rate, FS/4. This allows the chip to function as a digital down
converter when the filter stages are configured as a low-pass
filter.
The serial interface for 3- input and output data is compatible
with the serial ports of common DSP microprocessors.
Coefficients and configuration data are loaded over a
bidirectional eight bit interface.
Features
45MHz Clock Rate
256 Tap Programmable FIR Filter
24-Bit Data, 32-Bit Coefficients
Cascade of up to 5 Half Band Filters
Decimation from 1 to 256
Two Pin Interface for Down Conversion by FS/4
Multiplier for Mixing or Scaling Input with an External
Source
Serial I/O Compatible with Most DSP Microprocessors
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Low Cost FIR Filter
Filter Co-Processor
Digital Tuner
Block Diagram
Ordering Information
PART NUMBER
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
PKG. NO.
HSP43124SC-45
0 to +70
28 Ld SOIC (300 mil)
M28.3
HSP43124SC-45Z (Note) HSP43124SC-45Z
0 to +70
28 Ld SOIC (300 mil, Pb-free)
M28.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PROGRAM
MABL
E
FIR
FILTER
INPUT
F
O
RMA
TTER
DIN
SCLK
SYNCIN
MXIN
SYNCMX
OU
T
P
U
T
FORM
ATTER
DOUT
SYNCOUT
CLKOUT
A0-2
C0-7
WR
CONTROL
INTERFACE
RD
FSYNC
FCLK
HALF
BAND
FILTER
#5
HALF
BAND
FILTER
#2
HALF
BAND
FILTER
#1
Data Sheet
April 18, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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