参数资料
型号: HUFA76419D3S
厂商: Fairchild Semiconductor
文件页数: 2/10页
文件大小: 0K
描述: MOSFET N-CH 60V 20A DPAK
产品培训模块: High Voltage Switches for Power Processing
标准包装: 75
系列: UltraFET™
FET 型: MOSFET N 通道,金属氧化物
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 60V
电流 - 连续漏极(Id) @ 25° C: 20A
开态Rds(最大)@ Id, Vgs @ 25° C: 37 毫欧 @ 20A,10V
Id 时的 Vgs(th)(最大): 3V @ 250µA
闸电荷(Qg) @ Vgs: 27.5nC @ 10V
输入电容 (Ciss) @ Vds: 900pF @ 25V
功率 - 最大: 75W
安装类型: 表面贴装
封装/外壳: TO-252-3,DPak(2 引线+接片),SC-63
供应商设备封装: D-Pak
包装: 管件
HUFA76419D3, HUFA76419D3S
Electrical Specifications
T C = 25 o C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BV DSS
I DSS
I GSS
I D = 250 μ A, V GS = 0V (Figure 12)
I D = 250 μ A, V GS = 0V , T C = -40 o C (Figure 12)
V DS = 55V, V GS = 0V
V DS = 50V, V GS = 0V, T C = 150 o C
V GS = ± 16V
60
55
-
-
-
-
-
-
-
-
-
-
1
250
± 100
V
V
μ A
μ A
nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
V GS(TH)
r DS(ON)
V GS = V DS , I D = 250 μ A (Figure 11)
I D = 20A, V GS = 10V (Figures 9, 10)
I D = 20A, V GS = 5V (Figure 9)
I D = 19A , V GS = 4.5V (Figure 9)
1
-
-
-
-
0.031
0.036
0.038
3
0.037
0 . 043
0.046
V
?
?
?
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
R θ JC
R θ JA
TO-251,TO-252
-
-
-
-
2.00
100
o C/W
o C/W
Ambient
SWITCHING SPECIFICATIONS (V GS = 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t ON
t d(ON)
t r
t d(OFF)
t f
t OFF
V DD = 30V, I D = 19A
V GS = 4.5V, R GS = 13 ?
(Figures 15, 21, 22)
-
-
-
-
-
-
-
12
124
28
50
-
205
-
-
-
-
115
ns
ns
ns
ns
ns
ns
SWITCHING SPECIFICATIONS (V GS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t ON
t d(ON)
t r
t d(OFF)
t f
t OFF
V DD = 30V, I D = 20A
V GS = 10V,
R GS = 13 ?
(Figures 16, 21, 22)
-
-
-
-
-
-
-
6.5
35
50
50
-
62
-
-
-
-
150
ns
ns
ns
ns
ns
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q g(TOT)
Q g(5)
Q g(TH)
Q gs
Q gd
V GS = 0V to 10V
V GS = 0V to 5V
V GS = 0V to 1V
V DD = 30V,
I D = 20A,
I g(REF) = 1.0mA
(Figures 14, 19, 20)
-
-
-
-
-
23
12.5
0.9
2.7
5.9
27.5
15
1.05
-
-
nC
nC
nC
nC
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C ISS
C OSS
C RSS
V DS = 25V, V GS = 0V,
f = 1MHz
(Figure 13)
-
-
-
900
250
45
-
-
-
pF
pF
pF
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
V SD
t rr
Q RR
TEST CONDITIONS
I SD = 20A
I SD = 10A
I SD = 20A, dI SD /dt = 100A/ μ s
I SD = 20A, dI SD /dt = 100A/ μ s
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.0
74
200
UNITS
V
V
ns
nC
?2001 Fairchild Semiconductor Corporation
HUFA76419D3, HUFA76419D3S Rev. B
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