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参数资料
| 型号： | HUFA76419D3S |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 8/10页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 60V 20A DPAK |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 标准包装： | 75 |
| 系列： | UltraFET™ |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 60V |
| 电流 - 连续漏极(Id) @ 25° C： | 20A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 37 毫欧 @ 20A，10V |
| Id 时的 Vgs(th)（最大）： | 3V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 27.5nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 900pF @ 25V |
| 功率 - 最大： | 75W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | D-Pak |
| 包装： | 管件 |
HUFA76419D3, HUFA76419D3S
SABER Electrical Model
REV 8 July 1999
template HUFA76419d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 8.51e-13, cjo = 1.06e-9, tt = 4.90e-8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 7.42e-10, is = 1e-30, m = 0.85 )
m..model mmedmod = (type=_n, vto = 1.98, kp = 2.10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.33, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.75, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.0, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.1)
10
DPLCAP
5
LDRAIN
DRAIN
2
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.1, voff = -0.2)
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.2e-9
c.cin n6 n8 = 8.49e-10
RSLC2
RSLC1
51
ISCL
RDBREAK
72
RLDRAIN
RDBODY
i.it n8 n17 = 1
l.lsource n3 n7 = 3.57e-9
9
20
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
LGATE
GATE
l.ldrain n2 n5 = 1.0e-9 1
l.lgate n1 n9 = 2.51e-9
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
-
ESG
+
EVTEMP
RGATE + 18 -
22
6
8
6
EVTHRES
+ 19 -
8
CIN
50
RDRAIN
16
21
MMED
MSTRO
8
DBREAK
11
MWEAK
EBREAK
+
17
18
-
RSOURCE
7
71
DBODY
LSOURCE
RLSOURCE
SOURCE
3
res.rbreak n17 n18 = 1, tc1 = 1.14e-3, tc2 = 1.02e-9
res.rdbody n71 n5 = 1.03e-2, tc1 = 1.08e-3, tc2 = 9.91e-7
res.rdbreak n72 n5 = 2.39e-1, tc1 = 1.23e-4, tc2 = 1.11e-6
12
S1A
13
8
S2A
14
13
15
17
RBREAK
18
res.rdrain n50 n16 = 1.12e-2, tc1 = 1.19e-2, tc2 = 3.22e-5
S1B
S2B
RVTEMP
res.rgate n9 n20 = 3.12
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 25.1
res.rlsource n3 n7 = 35.7
res.rslc1 n5 n51 = 1e-6, tc1 = 9.91e-4, tc2 =3.17e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.60e-2, tc1 = 1e-3, tc2 =0
res.rvtemp n18 n19 = 1, tc1 = -1.45e-3, tc2 = 0
CA
13
+
EGS
-
6
8
CB
+
EDS
-
5
8
14
8
IT
RVTHRES
19
-
VBAT
+
22
res.rvthres n22 n8 = 1, tc1 = -2.34e-3, tc2 = -5.33e-6
spe.ebreak n11 n7 n17 n18 = 68.35
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))
}
}
?2001 Fairchild Semiconductor Corporation
HUFA76419D3, HUFA76419D3S Rev. B
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