参数资料
型号: HY5DU561622DT-6
厂商: HYNIX SEMICONDUCTOR INC
元件分类: DRAM
英文描述: 16M X 16 DDR DRAM, 0.7 ns, PDSO66
封装: 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件页数: 9/28页
文件大小: 814K
代理商: HY5DU561622DT-6
Rev. 0.6 / Mar. 2005
17
HY5DU561622DT
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
RFU
DR
TM
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
000
Reserved
001
2
010
4
011
8
100
Reserved
101
Reserved
110
Reserved
111
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency
000
Reserved
001
Reserved
010
Reserved
011
3
100
4
101
Reserved
110
Reserved
111
Reserved
A7
Test Mode
0Normal
1Test
A8
DLL Reset
0No
1Yes
BA0
MRS Type
0MRS
1EMRS
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