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| 型号： | HY5PS1G421LM-E3 |
| 厂商： | HYNIX SEMICONDUCTOR INC |
| 元件分类： | DRAM |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 256M X 4 DDR DRAM, 0.6 ns, PBGA63 |
| 封装： | FBGA-63 |
| 文件页数： | 29/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G421LM-E3 |
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Rev. 0.2 / Oct. 2005
29
1
HY5PS12421(L)M
HY5PS12821(L)M
2.5.3 Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the
rising edge of the clock. The address inputs determine the starting column address for the burst. The delay
from the start of the command to when the data from the first cell appears on the outputs is equal to the
value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data
(DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data
strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source
synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined
by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the
Extended Mode Register Set (1)(EMRS(1)).
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on
the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in
system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In
single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at
V
REF
. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation.
t
CH
t
CL
CK
CK
CK
DQS/DQS
DQ
DQS
DQS
t
RPST
Q
t
RPRE
t
DQSQmax
t
QH
t
QH
t
DQSQmax
Figure YY-- Data output (read) timing
Q
Q
Q
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
NOP
CK/CK
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
READ A
Posted CAS
AL = 2
CL =3
RL = 5
DQS/DQS
=< t
DQSCK
T0
T2
T1
T3
T4
T5
T6
T7
T8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G421M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G421M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G431AFP | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
| HY5PS1G431AFP-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM |
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