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参数资料
| 型号： | HY5PS1G821LM |
| 厂商： | Hynix Semiconductor Inc. |
| 英文描述： | 1Gb DDR2 SDRAM(DDP) |
| 中文描述： | 1G DDR2内存（铂） |
| 文件页数： | 25/79页 |
| 文件大小： | 1109K |
| 代理商： | HY5PS1G821LM |
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Rev. 0.2 / Oct. 2005
25
1
HY5PS12421(L)M
HY5PS12821(L)M
2.4 Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses BA0 ~ BA2 are used to select the desired bank. The row address A0
through A15 is used to determine which row to activate in the selected bank. The Bank Activate command
must be applied before any Read or Write operation can be executed. Immediately after the bank active
command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W
command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be
programmed into the device to delay when the R/W command is internally issued to the device. The additive
latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are sup-
ported. Once a bank has been activated it must be precharged before another Bank Activate command can
be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respec-
tively. The minimum time interval between successive Bank Activate commands to the same bank is deter-
mined by the RAS cycle time of the device (t
RC
). The minimum time interval between Bank Activate
commands is t
RRD
.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
ADDRESS
CK / CK
T0
T2
T1
T3
Tn
Tn+1
Tn+2
Tn+3
COMMAND
Bank A
Row Addr.
Bank A
Activate
Bank A
Col. Addr.
CAS-CAS delay time (
t
CCD
)
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Internal RAS-CAS delay (>=
t
RCDmin
)
: “H” or “L”
RAS Cycle time (
>= t
RC
)
additive latency delay (
AL
)
Read
Bank B
Row Addr.
Bank B
Activate
Bank B
Col. Addr.
Bank A
Addr.
Bank A
Precharge
Bank B
Addr.
Bank B
Precharge
Bank A
Row Addr.
Activate
Bank A
RAS - RAS delay time (
>= t
RRD
)
Read Begins
tRCD =1
Bank Active
(>= t
RAS
)
Bank Precharge time (
>= t
RP
)
Bank A
Post CAS
Bank B
PRead
相关PDF资料 |
PDF描述 |
|---|---|
| HY5PS1G821LM-C4 | 1Gb DDR2 SDRAM(DDP) |
| HY6264A-15 | RES 2.74 KOHM 1.0 % 2010S |
| HY6264A | 8KX8-Bit CMOS SRAM |
| HY6264A-10 | 8KX8-Bit CMOS SRAM |
| HY6264A-12 | 8KX8-Bit CMOS SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HY5PS1G821LM-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821LM-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M-C4 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
| HY5PS1G821M-E3 | 制造商:HYNIX 制造商全称:Hynix Semiconductor 功能描述:1Gb DDR2 SDRAM(DDP) |
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