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| 型号： | IBM0116160 |
| 厂商： | IBM Microeletronics |
| 英文描述： | 1M x 16 12/8 DRAM(16M位 动态RAM（带20条地址线，其中12条为行地址选通，8条为列地址选通）) |
| 中文描述： | 100万× 16 12 / 8的DRAM（1,600位动态随机存储器（带20条地址线，其中12条为行地址选通，8条为列地址选通）） |
| 文件页数： | 26/27页 |
| 文件大小： | 489K |
| 代理商： | IBM0116160 |
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IBM0116160
IBM0116160B
1M x 16 12/8 DRAM
IBM0116160M
IBM0116160P
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 26 of 27
43G9618
SA14-4207-06
Revised 4/97
Revision Log
Revision
Contents Of Modification
11/93
Initial Release
09/06/94
Combine the 3.3 Volt and the 5.0 Volt specifications
11/15/95
1. Iout changed to +2.0 mA and -2.0 mA in DC Electrical Characteristics table.
2. Packaging diagrams modified to clarify lead thickness and standoff height.
3. t
RPC
min changed from 0 to 5ns.
4. t
CHR
min changed from 20 to 10ns.
5. Currents in DC Electrical Characteristics table revised.
6. Test Modes and Test Circuit Diagram removed.
7. Rename t
ODD
to t
OED
.
8. t
OED,
t
CDD,
t
OEZ,
and t
OFF
min changed from 20 to 15ns, for the 70ns part.
9. t
RRH
min changed from 5 to 0ns for all speed sorts.
10. t
OEH
min changed from 20 to 15ns for the 70ns part.
11. t
CSR
min changed from 10 to 5ns for all speed sorts.
12. t
CAH
min changed from 15 to 10ns on 60 and 70ns parts.
13. t
OFF
max changed from 20 to 15ns for 70ns parts.
14. 400mil 42/42 SOJ package option added
12/10/95
1. The Low Power and Standard Power Specifications were combined. ES# 43G9174 and ES# 43G9618 were
combined into ES# 43G9618.
2. Added Die Rev E part numbers.
3. t
DH
was reduced from 15ns to 12ns for the -60 speed sort.
4. t
CHD
was added to the Self Refresh Cycle with a value of 350
μ
s for all speed sorts.
5. The Self Refresh timing was changed to allow CAS to go high t
CHD
after RAS falls entering a Self Refresh.
6. The CBR timing diagram was changed to allow CAS to remain low for back-to-back CBR cycles.
7. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “L” to ” H”.
09/01/96
1. I
CC2
was changed from 2mA to 1mA.
2. I
I(L)
and I
O(L)
were altered from +/- 10uA to +/- 5uA.
3. t
T
was initially at a max of 30ns. It has been modified to 50ns for all speed sorts.
4. t
CPA
was decreased from 30ns to 28ns for the -50 speed sort.
5. t
RASP
max of 125K was raised to 200K for all speed sorts.
6. t
RP
was changed from 35ns to 30ns for the -50 speed sort.
03/19/97
1. WE for the Hidden Refresh Write cycle in the Truth Table was changed from “H” to “L
→
H”.
2. t
OED
was moved from the Common Parameters table to the Write Cycle Parameters Table.
3. t
ODD
in the CAS before RAS timing diagram was renamed t
OED
.
4. The -70 speed sort and timings were removed.
5. I
cc1
, I
cc3
, I
cc6
for the -50 speed sort were reduced from 85mA to 50mA.
6. I
cc4
for the -50 speed sort was reduced from 75mA to 25mA.
7. I
cc1
, I
cc3
, I
cc6
for the -60 speed sort were reduced from 75mA to 45mA.
8. I
cc4
for the -60 speed sort was reduced from 65mA to 25mA.
04/23/97
1. I
cc5
was changed from 200
μ
A to 100
μ
A for the Low Power Die Rev F Parts.
Discontinued (9/98 - last order; 3/99 last ship)
相关PDF资料 |
PDF描述 |
|---|---|
| IBM0116160B | 1M x 16 12/8 DRAM(16M位 动态RAM（带20条地址线，其中12条为行地址选通，8条为列地址选通）) |
| IBM0116160M | 1M x 16 12/8 DRAM(16M位 动态RAM（带20条地址线，其中12条为行地址选通，8条为列地址选通）) |
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