参数资料
型号: IBM25PPC405GPR3BB400Z
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456
封装: 35 X 35 MM, ENHANCED, PLASTIC, BGA-456
文件页数: 47/58页
文件大小: 1264K
代理商: IBM25PPC405GPR3BB400Z
Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
3/14/03
Page 51 of 58
External Master Peripheral Interface
BusReq
na
6.1
2.2
10.3
7.1
PerClk
5
ExtAck
na
5.9
2.1
10.3
7.1
PerClk
5
ExtReq
4.1
0
na
PerClk
5
ExtReset
na
6
1
15.3
10.2
PerClk
5
HoldAck
na
6.1
2
10.3
7.1
PerClk
5
HoldPri
2.1
0
na
PerClk
5
HoldReq
3.1
0
na
PerClk
5
PerClk
na
0.7
-0.5
15.3
10.2
SysClk
4, 5
PerErr
2.4
0
na
PerClk
5
I/O Specifications—Group 2 (Part 2 of 2)
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the
PPC405GPr IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes
loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal
wiring.
4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is
selected. Refer to the
PowerPC 405GPr Embedded Processor User’s Manual for more information.
5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10%
and 90% points of the output voltage.
6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
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