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参数资料
| 型号： | ICS1527G-60LFTR |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, LEAD FREE, TSSOP-16 |
| 文件页数： | 11/11页 |
| 文件大小： | 620K |
| 代理商： | ICS1527G-60LFTR |
MDS1527 E
9
Revision 060204
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201
www.icst.com
Section 5 AC/DC Operating Conditions
ICS1527 Data Sheet
Table 5-4 AC Characteristics
Parameter
Symbol
Min.
Typical
Max.
Units
Notes
General
VCO Frequency
fVCO
50
400
MHz
VCO Gain
K
165
MHz/V
AC Inputs
EXTFB Input Frequency
fEXTFB
8
10,000
kHz
EXTFB Input High Voltage
VIH
2.0
V
EXTFB Input Low Voltage
VIL
1.0
V
Analog Input (HSYNC/VSYNC)
HSYNC Input Frequency
fHSYNC
8
10,000
kHz
VSYNC Input Frequency
fVSYNC
30
120
Hz
Input High Voltage
VIH
1.7
5.5
V
Input Low Voltage
VIL
VSS - 0.3
1.1
V
Input Hysteresis
0.2
0.8
V
Schmitt trigger active
SDA, SCL Digital Inputs
Input High Voltage
VIH
25.5
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
I2CADDR Digital Input
Input High Voltage
VIH
2
VDD+0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
SDA Digital Output
SDA Output Low Voltage
VOL
0.4
V
IOUT = 3 mA
SDA Output High Voltage
VOH
6.0
V
Determined by
external Rset resistor
LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)
Output Frequency,
ICS1527-110GLF
Fs
2.5
110
MHz
VDDD = 3.3 V
Output Frequency,
ICS1527-60GLF
Fs
2.5
60
MHz
VDDD = 3.3 V
Duty Cycle
SDC
45
50
55
%
2
Jitter, STJ, RMS
STJ
0.027
ns
30 kHz input to 50
MHz output
Jitter, STJ, pk-pk
STJ
0.200
ns
Jitter, Input-Output
IOJ
2.500
ns
HSYNC in to CLK out
Output Low Voltage
VOL
0.4
V
IOUT = 4 mA
Output High Voltage
VOH
2.4
V
IOUT = -4 mA
HSYNC to HSYNC_out
propagation delay (without
Schmitt-trigger)
29
ns
1
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