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参数资料
| 型号： | ICS1527G-60LFTR |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 4.40 MM, 0.65 MM PITCH, LEAD FREE, TSSOP-16 |
| 文件页数： | 6/11页 |
| 文件大小： | 620K |
| 代理商： | ICS1527G-60LFTR |
MDS 1527 E
4
Revision 060204
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201
www.icst.com
Section 2 Pin Descriptions
ICS1527 Data Sheet
Section 2 Pin Descriptions
Notes: 1. These LVTTL inputs are 5 V tolerant.
2. Connect to ground if unused.
Table 2-1
ICS1527 Pin Descriptions
PIN NO. PIN NAME
TYPE
DESCRIPTION
COMMENTS
Notes
1
VSSD
POWER
Digital ground
2SDA
IN/OUT
Serial data
I2C-bus
1
3SCL
IN
Serial clock
I2C-bus
1
4
VSYNC
IN
Vertical sync
1 & 2
5
EXTFB
IN
External feedback
From External Divider
1 & 2
6HSYNC
IN
Horizontal sync
Clock input to PLL
1 & 2
7VDDA
POWER
Analog supply
Power for analog circuitry
8
VSSA
POWER
Analog ground
Ground for analog circuitry
9I2CADR
IN
I2C device address
Chip I2C address select
10
LOCK
LVCMOS
OUT
Lock
PLL lock
11
HSYNC_out
LVCMOS
OUT
HSYNC output
Schmitt-trigger filtered HSYNC
realigned with the output pixel clock
12
CLK
LVCMOS
OUT
Pixel clock output
LVCMOS driver for full-speed clock
13
VDDQ
POWER
Output driver supply
Power for output drivers
14
VSYNC_out
LVCMOS
OUT
VSYNC output
Schmitt-trigger filtered VSYNC
realigned with the output pixel clock
15
VSSQ
POWER
Output driver ground
Ground for output drivers
16
VDDD
POWER
Digital supply
Power for digital sections
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