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参数资料
| 型号： | ICS1562BM-201T |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 产品变化通告： | Product Discontinuation 13/May/2009 |
| 标准包装： | 2,500 |
| 类型： | 时钟/频率合成器，时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，TTL，晶体 |
| 输出： | CMOS，PECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:3 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | 1562BM-201T |
BIT(S)
BIT REF.
DESCRIPTION
13-14
S[0]..S[1]
PLL post-scaler/test mode select bits.
S[1] S[0]
DESCRIPTION
0
Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0
1
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1
0
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder
drives the LOAD output which, in turn, drives the N2 divider.
1
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
15
AUX_CLK
When in the AUXEN clock mode, this bit controls the differential outputs.
16
AUX_N1
When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming). When not in
the AUXEN clock mode, this bit, if set to one, will override the N1 divider
modulus and output the VCO frequency divided by two [F(PLL)/2] at the
LOAD output.
17-24
N2[0]..N2[7]
Sets the modulus of the N2 divider. The input of the N2 divider is the
28
N2[8]
output of the N1 divider in all clock modes except AUXEN.
25-27
V[0]..V[2]
Sets the gain of VCO according to this table.
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
100
30
101
45
110
60
111
80
29-30
P[0]..P[1]
Sets the gain of the phase detector according to this table.
P[1]
P[0]
GAIN (uA/radian)
00
0.05
01
0.15
10
0.5
11
1.5
31
RESERVED
Set to zero.
32
P[2]
Phase detector tuning bit. Should normally be set to one.
ICS1562B
12
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS1562BM-XXX | 制造商:ICS 制造商全称:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1567 | 制造商:ICS 制造商全称:ICS 功能描述:Differential Output Video Dot Clock Generator |
| ICS1567-742 | 制造商:ICS 制造商全称:ICS 功能描述:Differential Output Video Dot Clock Generator |
| ICS1567M-742 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Video/Graphics Clock Generator |
| ICS1572 | 制造商:ICS 制造商全称:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
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